Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 3: Client Interface
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
CLIENTEMAC#RXCLIENTCLKIN
PHYEMAC#RXCLK
(CLIENTEMAC#RXCLIENTCLKIN/2)
DA SA DATA
Figure 3-21: 16-Bit Receive (Even Byte Case)
Figure 3-22 shows the timing of a normal inbound frame transfer for the case with an odd
number of bytes in the frame.
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLD MSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
DA SA DATA
Figure 3-22: 16-Bit Receive (Odd Byte Case)
UG194_3_21_072106
UG194_3_22_072106
As shown in Figure 3-21 and Figure 3-22, EMAC#CLIENTRXDVLDMSW is used to denote an
odd number of bytes in the frame. The data valid signals are shown in the even byte case
(Figure 3-21). In the odd byte case (Figure 3-22), EMAC#CLIENTRXDVLDMSW is deasserted
one clock cycle earlier compared to the EMAC#CLIENTRXDVLD signal, after the reception of
the frame. EMAC#CLIENTRXD[7:0] contains the data in this odd byte case.
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UG194 (v1.10) February 14, 2011
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