Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
Virtex-4 to Virtex-5 FPGA
Enhancements
New Features
Appendix C
The Virtex®-5 Embedded Tri-Mode Ethernet MAC is derived from the Virtex-4 FPGA
Embedded Tri-mode Ethernet MAC with some key enhancements and a few minor
modifications, as documented in this appendix.
The Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC is a stand-alone block located in
the block RAM columns. It is no longer resides inside in the processor block, as is the case
for Virtex-4 FPGA Ethernet MACs.
Unidirectional Enable
Unidirectional enable is a new mode that allows Ethernet MAC to transmit even while
there is a loss of synchronization at the receiver (1000BASE-X PCS/PMA or SGMII modes).
This mode can be turned on/off via an MDIO write and its value can be read from bit 0.5
in the PCS Configuration Register 0. This bit is also new in the IEEE 802.3 specification and
was previously reserved. The default value of this register bit is set by the
EMAC#_UNIDIRECTION_ENABLE attribute, as described in “Additional Attributes,”
page 221.
Programmable Auto-Negotiation Link Timer
GT Loopback
A programmable link timer interrupt value for auto-negotiation is available in the Virtex-5
FPGA Ethernet MAC for 1000BASE-X PCS/PMA or SGMII modes. This value is set using
the EMAC#_LINKTIMERVAL[8:0] attribute, as described in “Additional Attributes,” page
221.
This mode allows the position of the loopback to be selected between loopback in the
RocketIO serial transceiver or a loopback internal to the Ethernet MAC. This is
applicable for 1000BASE-X PCS/PMA or SGMII modes only. When the loopback is
internal to the Ethernet MAC, a constant stream of Idle code groups are transmitted
through the RocketIO serial transceiver. The EMAC#_GTLOOPBACK attribute, as
described in “Additional Attributes,” page 221, can be used to select the default position of
the loopback.
TEMAC User Guide www.xilinx.com 217
UG194 (v1.10) February 14, 2011