Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 3: Client Interface Statistics Vectors Transmitter Statistics Vector CLIENTEMAC#TXCLIENTCLKIN TX_STATISTICS_VALID (internal signal) TX_STATISTICS_VECTOR[31:0] (internal signal) EMAC#CLIENTTXSTATSVLD EMAC#CLIENTTXSTATS TX_STATISTICS_VECTOR contains the statistics for the frame transmitted. The TX_STATISTICS_VECTOR is a 32-bit vector and an internal signal. This vector is muxed out to a one-bit signal, EMAC#CLIENTTXSTATS, as shown in Figure 3-31 , following frame transmission. For standard clock management, the vector is driven synchronously by the transmitter clock, CLIENTEMAC#TXCLIENTCLKIN. For alternative clock management, including the use of clock enables, the vector is driven synchronously to other TX client logic signals. See Chapter 6, “Physical Interface,” for relevant clocking networks. The bit-field definition for the transmitter statistics vector is defined in Table 3-3, page 80. 0 1 2 3 4 5 28 29 30 31 Figure 3-31: Transmitter Statistics Mux Timing UG194_03_31_072106 The block diagram for the transmitter statistics MUX in the Ethernet MAC is shown in Figure 3-32. 78 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Ethernet MAC Block EMAC#CLIENTTXSTATSBYTEVLD Ethernet MAC TX_STATISTICS_VECTOR[31:0] (Internal Signal) CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXCLIENTCLKIN TXSTATSMUX TXSTATSDEMUX User-Defined Statistics Processing Block Figure 3-32: Transmitter Statistics MUX Block Diagram Statistics Vectors TX_STATISTICS_VALID (Internal Signal) UG194_3_32_071509 All bit fields in EMAC#CLIENTTXSTATS are only valid when EMAC#CLIENTTXSTATSVLD is asserted as illustrated in Figure 3-33. EMAC#CLIENTTXSTATSBYTEVLD is asserted if an Ethernet MAC frame byte (DA to FCS inclusive) is being transmitted. The signal is valid on every CLIENTEMAC#TXCLIENTCLKIN cycle. TX_STATISTICS_VECTOR (bits 28 down to 20 inclusive) are only for half-duplex mode. When operating in full-duplex mode, these bits are reset to a logic 0. TEMAC User Guide www.xilinx.com 79 UG194 (v1.10) February 14, 2011 [31:0] EMAC#CLIENTTXSTATS RESET TXSTATSVEC [31:0] EMAC#CLIENTTXSTATSVLD TXSTATSVLD FPGA Logic
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77: R Operation Figure 3-30 illustrates
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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