Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Appendix C: Virtex-4 to Virtex-5 FPGA Enhancements Tie-Off Pins Changed to Attributes The Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC has 80 tie-off pins (TIEEMAC#CONFIGVEC[79:0]) that can be used to configure the Ethernet MAC at power-up or when the Ethernet MAC is reset. In the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC, these 80 tie-off pins have been replaced with attributes. Table C-2 shows how the Virtex-5 FPGA attributes relate to the Virtex-4 FPGA tie-off pins. Table C-2: Mapping Tie-Off Pin Names to Attribute Names Virtex-4 FPGA Tie-off Pin Name Virtex-5 FPGA Attribute Name TIEEMAC#CONFIGVEC[79] EMAC#_CONFIGVEC_79 TIEEMAC#CONFIGVEC[78] EMAC#_PHYRESET TIEEMAC#CONFIGVEC[77] EMAC#_PHYINITAUTONEG_ENABLE TIEEMAC#CONFIGVEC[76] EMAC#_PHYISOLATE TIEEMAC#CONFIGVEC[75] EMAC#_PHYPOWERDOWN TIEEMAC#CONFIGVEC[74] EMAC#_PHYLOOPBACKMSB TIEEMAC#CONFIGVEC[73] EMAC#_MDIO_ENABLE TIEEMAC#CONFIGVEC[72] EMAC#_SPEED_MSB TIEEMAC#CONFIGVEC[71] EMAC#_SPEED_LSB TIEEMAC#CONFIGVEC[70] EMAC#_RGMII_ENABLE TIEEMAC#CONFIGVEC[69] EMAC#_SGMII_ENABLE TIEEMAC#CONFIGVEC[68] EMAC#_1000BASEX_ENABLE TIEEMAC#CONFIGVEC[67] EMAC#_HOST_ENABLE TIEEMAC#CONFIGVEC[66] EMAC#_TX16BITCLIENT_ENABLE TIEEMAC#CONFIGVEC[65] EMAC#_RX16BITCLIENT_ENABLE TIEEMAC#CONFIGVEC[64] EMAC#_ADDRFILTER_ENABLE TIEEMAC#CONFIGVEC[63] EMAC#_LTCHECK_DISABLE TIEEMAC#CONFIGVEC[62] EMAC#_RXFLOWCTRL_ENABLE TIEEMAC#CONFIGVEC[61] EMAC#_TXFLOWCTRL_ENABLE TIEEMAC#CONFIGVEC[60] EMAC#_TXRESET TIEEMAC#CONFIGVEC[59] EMAC#_TXJUMBOFRAME_ENABLE TIEEMAC#CONFIGVEC[58] EMAC#_TXINBANDFCS_ENABLE TIEEMAC#CONFIGVEC[57] EMAC#_TX_ENABLE TIEEMAC#CONFIGVEC[56] EMAC#_TXVLAN_ENABLE TIEEMAC#CONFIGVEC[55] EMAC#_TXHALFDUPLEX TIEEMAC#CONFIGVEC[54] EMAC#_TXIFGADJUST_ENABLE TIEEMAC#CONFIGVEC[53] EMAC#_RXRESET 220 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Additional Attributes Table C-2: Mapping Tie-Off Pin Names to Attribute Names (Cont’d) Additional Attributes Virtex-4 FPGA Tie-off Pin Name Virtex-5 FPGA Attribute Name TIEEMAC#CONFIGVEC[52] EMAC#_RXJUMBOFRAME_ENABLE TIEEMAC#CONFIGVEC[51] EMAC#_RXINBANDFCS_ENABLE TIEEMAC#CONFIGVEC[50] EMAC#_RX_ENABLE TIEEMAC#CONFIGVEC[49] EMAC#_RXVLAN_ENABLE TIEEMAC#CONFIGVEC[48] EMAC#_RXHALFDUPLEX TIEEMAC#CONFIGVEC[47:0] EMAC#_PAUSEADDR[47:0] In addition to the tie-off pins being converted to attributes, six new parameters have been added to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC that are also controlled by attributes. The following list provides a brief summary: EMAC#_DCRBASEADDR[0:7]: Separate DCR base addresses are specified for each Ethernet MAC. EMAC#_UNIDIRECTION_ENABLE: Allows the Ethernet MAC to transmit even while loss of synchronization at the receiver (1000BASE-X PCS/PMA or SGMII mode). EMAC#_LINKTIMERVAL[8:0]: Programmable link timer interrupt value for autonegotiation (1000BASE-X PCS/PMA or SGMII mode). EMAC#_BYTEPHY: Optional advanced clocking scheme to reduce use of global clock resources. EMAC#_USECLKEN: Optional advanced clocking scheme to reduce use of global clock resources. This mode switches the client interface clock output to become a clock enable. EMAC#_GTLOOPBACK: Enables loopback in the RocketIO serial transceiver, otherwise an internal loopback is used (1000BASE-X PCS/PMA or SGMII mode). More detailed information can be found in Chapter 2. TEMAC User Guide www.xilinx.com 221 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217 and 218: R Virtex-4 to Virtex-5 FPGA Enhance
Page 219: R Clock Enables Modifications Relat
Page 223 and 224: R Appendix D Differences between So
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