Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
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Chapter 6: Physical Interface<br />
GTX_CLK<br />
If the CORE Generator tool is used, then the wrapper files for the <strong>Ethernet</strong> <strong>MAC</strong> that are<br />
created contain the logic described in these sections. By using the CORE Generator tool,<br />
the time required to instantiate the <strong>Ethernet</strong> <strong>MAC</strong> into a usable design is greatly reduced.<br />
See “Accessing the <strong>Ethernet</strong> <strong>MAC</strong> from the CORE Generator Tool,” page 25.<br />
RGMII Clock Management for 1 Gb/s Only<br />
IBUFG<br />
TX Client<br />
Logic<br />
RX Client<br />
Logic<br />
RGMII Version 1.3<br />
BUFG<br />
Figure 6-12 shows the clock management used with the RGMII interface when using the<br />
Hewlett Packard RGMII Specification v1.3. GTX_CLK must be provided to the <strong>Ethernet</strong> <strong>MAC</strong><br />
with a high-quality, 125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements. The<br />
E<strong>MAC</strong>#PHYTXGMIIMIICLKOUT output port drives all transmitter logic through a BUFG.<br />
X<br />
X<br />
E<strong>MAC</strong>#<br />
PHYE<strong>MAC</strong>#GTXCLK<br />
PHYE<strong>MAC</strong>#TXGMIIMIICLKIN<br />
E<strong>MAC</strong>#PHYTXGMIIMIICLKOUT<br />
CLIENTE<strong>MAC</strong>#TXCLIENTCLKIN<br />
E<strong>MAC</strong>#CLIENTTXCLIENTCLKOUT<br />
E<strong>MAC</strong>#PHYTXD[3:0]<br />
E<strong>MAC</strong>#PHYTXD[7:4]<br />
PHYE<strong>MAC</strong>#MIITXCLK<br />
CLIENTE<strong>MAC</strong>#RXCLIENTCLKIN<br />
E<strong>MAC</strong>#CLIENTRXCLIENTCLKOUT<br />
PHYE<strong>MAC</strong>#RXCLK<br />
PHYE<strong>MAC</strong>#RXD[3:0]<br />
PHYE<strong>MAC</strong>#RXD[7:4]<br />
CLIENTE<strong>MAC</strong>#DCMLOCKED<br />
Notes:<br />
1) A regional buffer (BUFR) can replace this BUFG.<br />
In addition, the clock input of IDDR can be driven by a BUFIO.<br />
Refer to UG190, <strong>Virtex</strong>-5 <strong>FPGA</strong> User Guide for BUFR usage guidelines.<br />
Figure 6-12: 1 Gb/s RGMII Hewlett Packard v1.3 Clock Management<br />
154 www.xilinx.com TE<strong>MAC</strong> User Guide<br />
<strong>UG194</strong> (v1.10) February 14, 2011<br />
X<br />
1<br />
0<br />
ODDR<br />
D1<br />
Q<br />
IDELAY<br />
OBUF<br />
IBUFG<br />
RGMII_RXC<br />
IDDR<br />
Q1 D IDELAY<br />
RGMII_RXD[3:0]<br />
Q2<br />
ODDR<br />
D1<br />
D2<br />
D2<br />
BUFG (1)<br />
Q<br />
OBUF<br />
IBUF<br />
RGMII_TXC<br />
RGMII_TXD[3:0]<br />
<strong>UG194</strong>_6_12_080409<br />
R