Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 4: Host/DCR Bus Interfaces
// Poll the RDYstatus_e1 register
while ( !(dcr_read(EMAC1_DCRBASEADDR + 3) & 0x00010000) );
Reading from the General Address Table Register of the Address Filter Block
The same methods used in reading and writing to the Ethernet MAC configuration
registers through the DCR apply to the address filter configuration registers. The only
operations that differ are reading and writing from the general address table.
To read the desired general address table register of the address filter, a DCR write
operation must be performed.
1. Write to the dataRegLSW register, setting the two-bit address of the general address
table of the register to be accessed (four general address table registers are in the
address filter block) and the RNW bit to 1.
2. Write to the cntlReg register with the address register of general address (Word 1) to
0x38C. Set the Write enable bit to write to the general address (Word 1) (see
Table 4-12). Use EMAC0_DCRBASEADDR to access EMAC0 and
EMAC1_DCRBASEADDR to access EMAC1.
3. Poll the RDYstatus_e# register until the address filter Read-Ready bit is set to 1 or wait
until the DCRHOSTDONEIR interrupt is asserted.
4. Read from the dataRegMSW to read the general address [47:32] and dataRegLSW to
read general address [31:0].
To read from the general address table register (2) of EMAC0:
// MULTI_ADDR Register 2 of AF Block
// Set the enable bit of the MULTI_ADDR RNW and MULTI_ADDR Register 2
dcr_write(EMAC0_DCRBASEADDR + 1, 0x00820000);
// Write the address of EMAC0 General Address register to the cntlReg
// register, with the write enable bit asserted
dcr_write(EMAC0_DCRBASEADDR + 2, 0x0000838C);
// Poll the RDYstatus_e0 register
while ( !(dcr_read(EMAC0_DCRBASEADDR + 3) & 0x00010000) );
// Read the values returned of the General Address Word0 and Word1
// registers (48-bit value)
// from the dataRegMSW and dataRegLSW registers
gen_addr_msw = dcr_read(EMAC0_DCRBASEADDR + 0);
gen_addr_lsw = dcr_read(EMAC0_DCRBASEADDR + 1);
Writing to the General Address Table Register of the Address Filter Block
The same methods used in reading and writing to the Ethernet MAC configuration
registers through the DCR apply to the address filter configuration registers. The only
operations that differ are reading and writing from the general address table.
For writing to the desired general address table register of the AF block, two write
operations must be performed:
1. Write to the dataRegLSW register the general address [31:0] to be stored on the desired
general address table register.
2. Write to the cntlReg# register with the address for general address word 0 (0x388),
setting the write enable bit. Use EMAC0_DCRBASEADDR to access EMAC0 and
EMAC1_DCRBASEADDR to access EMAC1.
3. Poll the RDYstatus_e# register until the address configuration write bit is set to 1.
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UG194 (v1.10) February 14, 2011
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