Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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TEMAC User Guide www.xilinx.com UG194 (v1.10) February 14, 2011
Table of Contents Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 User Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 1: Introduction Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical Ethernet Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ethernet Switch or Router. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ethernet Communications Port for an Embedded Processor . . . . . . . . . . . . . . . . . . . . 19 Ethernet Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet Sublayer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Frame Transmission and Interframe Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Using the Embedded Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Accessing the Ethernet MAC from the CORE Generator Tool . . . . . . . . . . . . . . . . . . . 25 Simulating the Ethernet MAC using SecureIP Models . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 2: Ethernet MAC Overview Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ethernet MAC Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ethernet MAC Primitive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ethernet MAC Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Client-Side Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Host Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Management Data Input/Output (MDIO) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MII/GMII/RGMII Physical Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RocketIO Serial Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Global Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Ethernet MAC Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Chapter 3: Client Interface Transmit (TX) Client: 8-Bit Interface (without Clock Enables) . . . . . . . . . . . . . . . . 52 Normal Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 In-Band Parameter Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Client-Supplied FCS Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Client Underrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Back-to-Back Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Virtual LAN (VLAN) Tagged Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TEMAC User Guide www.xilinx.com 7 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5: Date Version Revision 10/01/09 1.9
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58:
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60:
R Normal Frame Transmission PHYEMAC
Page 61 and 62:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
Page 67 and 68:
R Receive (RX) Client: 8-Bit Interf
Page 69 and 70:
R Receive (RX) Client: 16-Bit Inter
Page 71 and 72:
R Address Filtering Address Filteri
Page 73 and 74:
R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76:
R Transmitting a PAUSE Control Fram
Page 77 and 78:
R Operation Figure 3-30 illustrates
Page 79 and 80:
R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86:
R Host/DCR Bus Interfaces This chap
Page 87 and 88:
HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90:
R Table 4-3: Receiver Configuration
Page 91 and 92:
R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102:
R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114:
R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
Page 135 and 136:
R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138:
R Physical Interface Chapter 6 This
Page 139 and 140:
R GMII / MII RGMII SGMII Introducti
Page 141 and 142:
TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144:
R Gigabit Media Independent Interfa
Page 145 and 146:
GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148:
GTX_CLK R IBUFG BUFG TX Client Logi
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Page 151 and 152:
Page 153 and 154:
R Reduced Gigabit Media Independent
Page 155 and 156:
Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
Page 159 and 160:
GTX_CLK TX Client Logic RX Client L
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168:
R Ethernet MAC to RocketIO Serial T
Page 169 and 170:
TX and RX Client Logic R 1000BASE-X
Page 171 and 172:
R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174:
R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176:
R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178:
R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180:
FPGA R Introduction to the SGMII Im
Page 181 and 182:
R RX Elastic Buffer Implementations
Page 183 and 184:
R Serial Gigabit Media Independent
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192:
TX and RX Client Logic R SGMII Cloc
Page 193 and 194:
Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 197 and 198:
Page 199 and 200:
R Interfacing to a Statistics Block
Page 201 and 202:
R Using the DCR Bus to Access Stati
Page 203 and 204:
R Pinout Guidelines Appendix A Xili
Page 205 and 206:
R Ethernet MAC Clocks Appendix B Th
Page 207 and 208:
TX Client Logic RX Client Logic R
Page 209 and 210:
R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
Page 213 and 214:
R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216:
R Clock Definitions and Frequencies
Page 217 and 218:
R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220:
R Clock Enables Modifications Relat
Page 221 and 222:
R Additional Attributes Table C-2:
Page 223 and 224:
R Appendix D Differences between So
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