Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface Loopback itself can be enabled or disabled by writing to the PCS/PMA Sublayer Control Register (Register 0). The loopback position can be controlled through the Loopback Control Register (Register 17). See “1000BASE-X PCS/PMA Management Registers,” page 122 for details. Alternatively, loopback can be controlled by setting the EMAC#_PHYLOOPBACKMSB and EMAC#_GTLOOPBACK attributes. See Chapter 2 for details. Serial Gigabit Media Independent Interface (SGMII) Generic Host Bus DCR Bus Ethernet MAC PCS/PMA Sublayer Flow Control Interface Host Interface DCR Bridge Figure 6-27 shows the functional block diagram of the Ethernet MAC with the PCS/PMA sublayer block highlighted. EMAC# TX RX 16- or 8-Bit Client Interface Transmit Engine Flow Control Receive Engine Address Filter Registers MDIO Interface MAC Configuration Registers Figure 6-27: PCS/PMA Sublayer Block Diagram in the Ethernet MAC The PCS/PMA sublayer extends the functionality of the Ethernet MAC, replacing the GMII/MII or RGMII parallel interfaces with an interface to a RocketIO serial transceiver. The connected RocketIO serial transceiver then provides the remaining functionality to accommodate the following two standards, both of which require the high-speed serial interface provided by the RocketIO serial transceiver: “Serial Gigabit Media Independent Interface (SGMII)” “1000BASE-X PCS/PMA” TX RX Statistics Clock Management MII/GMII/RGMII Interface to External PHY GTP/GTX Transceiver Interface MDIO Interface to External PHY UG194_6_27_071709 178 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 MII/GMII/RGMII Interface TX RX TX RX PCS/PMA Sublayer PCS Management Registers MDIO Intersection R
FPGA R Introduction to the SGMII Implementation PCS/PMA Sublayer Serial Gigabit Media Independent Interface (SGMII) The Serial GMII (SGMII) is an alternative interface to the GMII/MII that converts the parallel interface of the GMII/MII into a serial format that is capable of carrying traffic at speeds of 10 Mb/s, 100 Mb/s, and 1 Gb/s. It radically reduces the I/O count and is, therefore, often favored by PCB designers. The SGMII physical interface was defined by Cisco Systems. The data signals operate at a rate of 1.25 Gb/s. Due to the speed of these signals, differential pairs are used to provide signal integrity and minimize noise. The sideband clock signals defined in the specification are not implemented in the Ethernet MAC. Instead, the RocketIO serial transceiver is used to transmit and receive the differential data at the required rate using clock data recovery (CDR). For more information on SGMII, refer to the Serial GMII specification v1.7. Figure 6-28 shows an expanded diagram of the PCS/PMA sublayer block. The Ethernet MAC is connected to a RocketIO serial transceiver, which in turn connects to a Tri-Speed Ethernet BASE-T PHY device via SGMII. MAC TX Interface MAC RX Interface MDIO Interface PCS Transmit Engine Auto-Negotiation PCS Receive Engine and Synchronization PCS Management Registers Figure 6-28: Ethernet PCS/PMA Sublayer Extension UG194_6_28_080409 The PCS/PMA sublayer contains its own functional blocks, which are illustrated and summarized in the following subsections. TEMAC User Guide www.xilinx.com 179 UG194 (v1.10) February 14, 2011 GTP/GTX Transceiver TX+ TX- RX+ RX- SGMII Link 10BASE-T 100BASE-T 1000BASE-T PHY PHY Link TX Copper Medium RX
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217 and 218: R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220: R Clock Enables Modifications Relat
Page 221 and 222: R Additional Attributes Table C-2:
Page 223 and 224: R Appendix D Differences between So
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