Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview On the physical side of the Ethernet MAC, a common MII/GMII/RGMII interface block is shown. When the physical interface of the Ethernet MAC is configured to MII/GMII or RGMII, these signals can be used via standard I/Os to connect to an external physical interface. When the physical interface is configured in 1000BASE-X or SGMII mode, the PCS/PMA sublayer block in the Ethernet MAC is enabled. The PCS/PMA sublayer block interfaces directly to the RocketIO serial transceiver. See “Physical Interface,” page 137 for information on all physical interfaces, including clocking schemes and interfacing with serial transceivers. The clock management module automatically configures the output clocks to the correct frequency based on the internal speed of the Ethernet MAC (10 Mb/s, 100 Mb/s, or 1000 Mb/s) and the Ethernet MAC mode settings (GMII, MII, RGMII, SGMII, and 1000BASE-X). Ethernet MAC Configuration Options The Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC addresses all common configuration requirements for embedded Ethernet connectivity. This section provides an overview of the possible options for each Ethernet MAC. A full list of the mode configuration options is in Table 2-16, and further details on the configuration options and how to set these using the CORE Generator tool can be found in “Accessing the Ethernet MAC from the CORE Generator Tool,” page 25. The choice of physical interface for the Ethernet MAC affects some of the other configuration options. Table 2-1 provides a breakdown of compatible parameters. Table 2-1: Ethernet MAC Block Static Configurations Physical Interface Client Interface Speed Advanced Clocking 8-Bit 16-Bit Tri- Speed 1G 10/100M Clock Enable Byte PHY MII only Y N N N Y Y N GMII only Y N N Y N N N GMII/MII Y N Y Y Y Y (Tri-speed) Y (Tri-speed) RGMII Y N Y Y Y Y (Tri-speed) N SGMII Y N Y Y Y N N 1000BASE-X Y Y N Y N N N A 16-bit client interface can only be used when the Ethernet MAC physical interface is configured to be 1000BASE-X. The 16-bit client interface allows the Ethernet MAC to run at an internal clock frequency of greater than 125 MHz. The Ethernet MAC can run at a line rate greater than 1 Gb/s, as specified in IEEE Std 802.3. Therefore, this interface should not be used for Ethernet compliant designs, but it can be useful for backplane applications. The possible speed configurations for the Ethernet MAC vary with the physical interface configuration. An initial value for the speed can be chosen for the Ethernet MAC at instantiation, and depending on the mode, this speed can later be modified by writing to the Ethernet MAC mode configuration register. 30 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Ethernet MAC Primitive Ethernet MAC Primitive To minimize resource utilization, advanced (optimized) clocking schemes are available for specific physical interface configurations. In addition to the configuration options listed in Table 2-1, it is also possible to statically configure other interfaces: Out of the pair of Ethernet MACs, either or both can be enabled. To use a single Ethernet MAC, a pair is instantiated and one can be disabled. The host interface can be enabled/disabled. This affects both Ethernet MACs. Per Ethernet MAC, the MDIO interface can be enabled/disabled. Within the paired Ethernet MACs, the individual MACs can have different configuration settings. The Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC is available to the Xilinx® software tools as a library primitive, named TEMAC. This primitive encompasses the Ethernet MAC block as illustrated in Figure 2-1; it includes a pair of Ethernet MACs (EMAC0 and EMAC1) sharing a common host interface. The Ethernet MAC primitive can be simplified for specific customer needs by using the CORE Generator tool to create Ethernet MAC wrappers. “Accessing the Ethernet MAC from the CORE Generator Tool,” page 25 describes how to use the CORE Generator software to simplify the Ethernet MAC primitive. Figure 2-3 illustrates the Tri-Mode Ethernet MAC primitive. The # sign denotes that a port of that name exists for each of the Ethernet MACs (EMAC0 and EMAC1) in the TEMAC primitive. TEMAC User Guide www.xilinx.com 31 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29: Generic Host Bus DCR Bus R Flow Con
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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