Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview Table 2-16: Mode Configuration Attributes (Cont’d) Attribute Type Description Attributes to Configure Fixed Speed for the Ethernet MAC These attributes determine the speed of the Ethernet MAC after reset or power-up. The speed of the Ethernet MAC can be changed in multi-speed configurations using the host interface, when the host interface is enabled. (The host interface is enabled by setting the EMAC#_HOST_ENABLE attribute to TRUE). If the host interface is not enabled, then the speed of the Ethernet MAC is directly set by these two attributes. (EMAC#_SPEED_MSB: EMAC#_SPEED_LSB) 1:0 = 1000 Mb/s 0:1 = 100 Mb/s 0:0 = 10 Mb/s 1:1 = not applicable See “Ethernet MAC Mode Configuration Register,” page 92 for register details. EMAC#_SPEED_MSB Boolean EMAC#_SPEED[1]. (TRUE takes the bit value 1 in the table cell above.) EMAC#_SPEED_LSB Boolean EMAC#_SPEED[0]. (TRUE takes the bit value 1 in the table cell above.) Attributes to Configure Advanced Clocking Scheme for the Ethernet MAC To reduce the number of BUFGs used for the Ethernet MAC, optimized clocking modes are available. See “Clock Connections to and from FPGA Logic,” page 206 for a description of the possible clocking mode options. EMAC#_BYTEPHY Boolean When this attribute is set to TRUE, the GMII/MII interface bus remains the same as GMII interface. Specifically, it is 8 bits wide and runs at the EMAC block’s ½ clock rate of 12.5 MHz or 1.25 MHz. See “Advanced Clocking Schemes,” page 208 for an introduction to this clocking mode option. EMAC#_USECLKEN Boolean When this attribute is set to TRUE, the client interface clock output is switched to clock enable, thus eliminating BUFGs on the client interface. See “Advanced Clocking Schemes,” page 208 for an introduction to this clocking mode option. 44 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Table 2-17: MAC Configuration Attributes Attribute Type Description Attribute to Configure Default Register Value for the Address Filter Mode Register Ethernet MAC Attributes The address filter can be enabled/disabled using the host interface, when the host interface is enabled. (The host interface is enabled by setting the EMAC#_HOST_ENABLE attribute to TRUE). If the host interface is not enabled, the address filter mode is fixed by the following attribute value. See “Address Filter Mode,” page 97 for register details. EMAC#_ADDRFILTER_ENABLE Boolean Address Filter Enable: This attribute sets the default value of the Promiscuous Mode enable bit in the Address Filter Mode register. Setting this attribute to TRUE enables the use of the address filter module in the Ethernet MAC. Attributes to Configure Default Register Value for the Flow Control Configuration Register The following two attributes configure the Ethernet MAC flow control module. See “Flow Control Configuration Register,” page 91 for register details. EMAC#_RXFLOWCTRL_ENABLE Boolean Receive Flow Control Enable: This attribute sets the default value of the Flow control enable (RX) bit in the Flow Control Configuration Register. When this attribute is set to TRUE and full-duplex mode is enabled, receive flow control is enabled. Any flow control frames received by the Ethernet MAC cause the transmitter operation to be inhibited. When this attribute is set to FALSE, any flow control frames received by the Ethernet MAC are passed on to the client. See “Flow Control Block,” page 73 for description of flow control functionality. EMAC#_TXFLOWCTRL_ENABLE Boolean Transmit Flow Control Enable: This attribute sets the default value of the Flow control enable (TX) bit in the Flow Control Configuration Register. When this attribute is set to TRUE and full-duplex mode is enabled, asserting the CLIENTEMAC#PAUSEREQ signal causes the Ethernet MAC to send a flow control frame out from the transmitter. When this attribute is set to FALSE, asserting the CLIENTEMAC#PAUSEREQ signal has no effect. Attributes to Configure Default Register Value for the Transmitter Configuration Register The following attributes configure the transmit engine of the Ethernet MAC. See “Transmitter Configuration Register,” page 90 for register details. EMAC#_TXRESET Boolean This attribute sets the default value of the Reset bit in the Transmitter Configuration Register. When this attribute is set to TRUE, the Ethernet MAC transmitter is reset. This reset also sets all of the transmitter configuration registers to their default values. TEMAC User Guide www.xilinx.com 45 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43: R Table 2-16: Mode Configuration At
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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