Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 3: Client Interface
Requirement for Flow Control
Figure 3-27 illustrates the requirement for flow control. The Ethernet MAC on the right
side of the figure has a reference clock slightly faster than the nominal 125 MHz. The
Ethernet MAC on the left side of the figure has a reference clock slightly slower than the
nominal 125 MHz. This results in the Ethernet MAC on the left side of the figure not being
able to match the full line rate of the Ethernet MAC on the right side (due to clock
tolerances). The left Ethernet MAC is illustrated as performing a loopback
implementation; this results in the FIFO filling up over time. Without flow control, this
FIFO eventually fills and overflows, resulting in the corruption or loss of Ethernet frames.
Application
Flow Control Basics
Client Logic
FIFO
Figure 3-27: Requirement for Flow Control
An Ethernet MAC transmits a pause control frame for the link partner to cease
transmission for a defined period of time. For example, the left Ethernet MAC of
Figure 3-27 initiates a pause request when the client FIFO (illustrated) reaches a nearly full
state.
An Ethernet MAC responds to received pause control frames by ceasing transmission of
frames for the period of time defined in the received pause control frame. For example, the
right Ethernet MAC of Figure 3-27 ceases transmission after receiving the pause control
frame transmitted by the left Ethernet MAC. In a well-designed system, the right Ethernet
MAC ceases transmission before the client FIFO of the left Ethernet MAC overflows. This
provides time to empty the FIFO to a safe level before normal operation resumes. It also
safeguards the system against FIFO overflow conditions and frame loss.
74 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
MAC
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125 MHz +100 ppm
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