Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview Table 2-15: CLIENTEMAC#DCMLOCKED Signal Signal Direction Description CLIENTEMAC#DCMLOCKED Input If a DCM is used to derive any of the clock signals, the LOCKED port of the DCM must be connected to the CLIENTEMAC#DCMLOCKED port. The Ethernet MAC is held in reset until CLIENTEMAC#DCMLOCKED is asserted High. If the RocketIO serial transceiver PLL is used, the PLLLKDET signal should be ANDed with the DCM LOCK signal. If a DCM is not used, both CLIENTEMAC#DCMLOCKED ports from EMAC0 and EMAC 1 must be tied High. If any Ethernet MAC is not used, CLIENTEMAC#DCMLOCKED must be tied to High. Ethernet MAC Attributes This section describes the attributes (control parameters) that are used to configure the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC. Some of these attributes control the static configuration of the Ethernet MAC and others are used to preconfigure the internal control registers. The values of these attributes are loaded into the Ethernet MAC at powerup or when the Ethernet MAC is reset (1) . The attributes are divided into five sections: mode configuration, MAC configuration, physical interface, address filter, and DCR base address attributes. The mode configuration attributes control the static behavior of the Ethernet MAC, including whether the Ethernet MAC has a host interface, the type of physical interface, the width of the client interface and whether the MDIO interface is enabled. These attributes are not dynamically reconfigurable. All other attributes described in Table 2-16 (unless stated otherwise) define default values for internal registers. If the host interface is not enabled on the Ethernet MAC, these attributes allow the user to set the internal control register defaults. If the host interface is enabled (by setting the EMAC#_HOST_ENABLE attribute to be TRUE), then the host interface can be used to dynamically change the associated register contents or to read the register contents. 1. An attribute value of TRUE is translated into a bit value of 1; a value of FALSE equals a bit value of 0. 42 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Table 2-16: Mode Configuration Attributes Attribute Type Description Attribute to Configure Default Register Values for Management Configuration Register Ethernet MAC Attributes See “Management Configuration Register,” page 94 for register details. The MDIO interface can be enabled/disabled using the host interface, when the host interface is enabled. (The host interface is enabled by setting the EMAC#_HOST_ENABLE attribute to TRUE). If the host interface is not enabled then the MDIO enable value is fixed by this attribute. EMAC#_MDIO_ENABLE Boolean When EMAC#_HOST_ENABLE is FALSE, setting this attribute to TRUE enables the use of MDIO in the Ethernet MAC. When EMAC#_HOST_ENABLE and EMAC#_MDIO_ENABLE are both TRUE, the MDIO interface is enabled when the MDIO enable bit is set in the Ethernet MAC Management Configuration Register. See “MDIO Interface,” page 115. Attributes to Configure Fixed Mode for the Ethernet MAC See “Ethernet MAC Mode Configuration Register,” page 92 for register details. EMAC#_HOST_ENABLE Boolean Setting this attribute to TRUE enables the use of the Ethernet MAC host interface via either the generic host bus or the DCR bus. EMAC#_TX16BITCLIENT_ENABLE Boolean When this attribute is set to TRUE, the TX client data interface is 16 bits wide. When this attribute is set to FALSE, the TX client data interface is 8 bits wide. EMAC#_RX16BITCLIENT_ENABLE Boolean When this attribute is set to TRUE, the RX client data interface is 16 bits wide. When this attribute is set to FALSE, the RX client data interface is 8 bits wide. Attributes to Configure Fixed Physical Interface for the Ethernet MAC The following three attributes define the physical interface of the Ethernet MAC. These attributes are mutually exclusive. If none of these three attributes is set to TRUE, then the physical interface is enabled for 10/100 MII and GMII modes. See “Ethernet MAC Mode Configuration Register,” page 92 for register details. EMAC#_RGMII_ENABLE Boolean Setting this attribute to TRUE enables the Ethernet MAC for RGMII mode. EMAC#_SGMII_ENABLE Boolean Setting this attribute to TRUE enables the Ethernet MAC for SGMII mode. EMAC#_1000BASEX_ENABLE Boolean Setting this attribute to TRUE enables the Ethernet MAC for 1000BASE-X mode. TEMAC User Guide www.xilinx.com 43 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41: R Table 2-12: PCS/PMA Signals Table
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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