Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 1: Introduction Ethernet Protocol Overview This section gives an overview of where the Ethernet MAC fits into an Ethernet system and provides a description of some basic Ethernet terminology. Ethernet Sublayer Architecture OSI Reference Model Layers Application Presentation Session Transport Network Data Link PHY - Physical Figure 1-3 illustrates the relationship between the OSI reference model and the Ethernet MAC, as defined in the IEEE 802.3 specification. The grayed-in layers show the functionality that the Ethernet MAC handles. Figure 1-3 also shows where the supported physical interfaces fit into the architecture. PCS - Physical Coding Sublayer PMA - Physical Medium Attachment PMD - Physical Medium Dependent PCS PMA PMD Medium 1000BASE-X (e.g., Optical Fiber Medium) Figure 1-3: IEEE 802_3.2002 Ethernet Model MAC and MAC CONTROL Sublayer LAN CSMA/CD Layers Higher Layers LLC-Logical Link Control MAC Control (Optional) MAC - Media Access Control Reconciliation MII - Media Independent Interface The Ethernet MAC is defined in the IEEE 802.3 specification in clauses 2, 3, and 4. A MAC is responsible for the Ethernet framing protocols described in “Ethernet Data Format” and error detection of these frames. The MAC is independent of and can connect to any type of physical layer device. The MAC Control sublayer is defined in the IEEE 802.3 specification, clause 31. This provides real-time flow control manipulation of the MAC sublayer. Both the MAC CONTROL and MAC sublayers are provided by the Ethernet MAC in all modes of operation. 20 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 PCS PMA PMD Medium 1000BASE-T 100BASE-T 10BASE-T (e.g., Copper Medium) GMII - Gigabit Media Independent Interface RGMII - Reduced Gigabit Media Independent Interface SGMII - Serial Gigabit Media Independent Interface GMII/MII RGMII SGMII UG194_1_03_072306 R
R Number of Bytes Physical Sublayers PCS, PMA, and PMD Ethernet Protocol Overview The combination of the Physical Coding Sublayer (PCS), the Physical Medium Attachment (PMA), and the Physical Medium Dependent (PMD) sublayer constitute the physical layers for the protocol. Two main physical standards are specified: Ethernet Data Format Number of Bytes Preamble Preamble BASE-T PHYs provide a link between the MAC and copper mediums. This functionality is not offered within the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC. However, external BASE-T PHY devices are readily available on the market. These can connect to the Ethernet MAC, using GMII/MII, RGMII, or SGMII interfaces. BASE-X PHYs provide a link between the MAC and (usually) fibre optic mediums. The Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC is capable of supporting the 1 Gb/s BASE-X standard; 1000BASE-X PCS and PMA sublayers can be offered by connecting the Ethernet MAC to a RocketIO serial transceiver. An optical transceiver can be directly connected to the RocketIO serial transceiver to complete the PMD sublayer functionality. Ethernet data is encapsulated in frames, as shown in Figure 1-4, for standard Ethernet frames. The fields in the frame are transmitted from left to right. The bytes within the frame are transmitted from left to right (from least significant bit to most significant bit unless specified otherwise). The Ethernet MAC can handle jumbo Ethernet frames where the data field can be much larger than 1500 bytes. 7 1 6 6 2 0 - 1500 0 - 46 4 Start of Frame Destination Delimiter (SFD) Address Source Address Length/ Type 64 - 1518 Bytes Figure 1-4: Standard Ethernet Frame Format Data Pad UG194_1_04_072306 The Ethernet MAC can also accept VLAN frames. The VLAN frame format is shown in Figure 1-5. If the frame is a VLAN type frame, the Ethernet MAC accepts four additional bytes. 7 1 6 6 2 2 2 0 - 1500 0 - 46 4 Start of Frame Destination Delimiter (SFD) Address Source Address 0x 8100 VLAN Tag Len/ Type Data Pad FCS 64 - 1522 bytes Figure 1-5: Ethernet VLAN Frame Format Ethernet pause/flow control frames can be transmitted and received by the Ethernet MAC. Figure 3-29, page 75 shows how a pause/flow control frame differs from the standard Ethernet frame format. The following subsections describe the individual fields of an Ethernet frame and some basic functionality of the Ethernet MAC. TEMAC User Guide www.xilinx.com 21 UG194 (v1.10) February 14, 2011 FCS UG194_1_05_020807
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19: R Typical Ethernet Application Over
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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Page 163 and 164:
Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
Page 209 and 210:
R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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