Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 3: Client Interface
As shown in Figure 3-12, CLIENTEMAC#TXDVLDMSW denotes an odd number of bytes in the
frame. In the odd byte case, CLIENTEMAC#TXDVLDMSW is deasserted one clock cycle earlier
than the CLIENTEMAC#TXDVLD signal, after the transmission of the frame. Otherwise, these
data valid signals are the same as shown in the even byte case (Figure 3-11).
Back-to-Back Transfers
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
(CLIENTEMAC#TXCLIENTCLKIN/2)
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
For back-to-back transfers, both CLIENTEMAC#TXDVLD and CLIENTEMAC#TXDVLDMSW must
be deasserted for one PHYEMAC#MIITXCLK (half the clock frequency of
CLIENTEMAC#TXCLIENTCLKIN) clock cycle after the first frame. In the following
PHYEMAC#MIITXCLK clock cycle, both CLIENTEMAC#TXDLVD and CLIENTEMAC#TXDVLDMSW
are asserted High to indicate that the first two bytes of the destination address of the
second frame is ready for transmission on CLIENTEMAC#TXD[15:0]. In 16-bit mode, this
one PHYEMAC#MIITXCLK clock cycle IFG corresponds to a 2-byte gap (versus a 1-byte gap in
8-bit mode) between frames in the back-to-back transfer.
Figure 3-13 shows the timing diagram for 16-bit transmit for an even-byte case, and
Figure 3-14 shows the timing diagram for an odd-byte case.
D(n-2), D(n-3) D(n), D(n-1) DA1, DA0 DA3, DA2 DA5, DA4
1st Frame IFG 2nd Frame
Figure 3-13: 16-Bit Transmit Back-to-Back Transfer (Even Byte Case)
UG194_3_13_072206
62 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
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