Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface SGMII Auto-Negotiation Virtex-5 FPGA Ethernet MAC Processor Overview of Operation Host Interface Figure 6-40 illustrates a simplified diagram of the Ethernet MAC instantiated within a Virtex-5 device. The only components shown are two of the PCS Management Registers, which are directly involved in the Auto-Negotiation process (see “SGMII Management Registers,” page 130). The corresponding registers of the connected devices are also shown. PCS/PMA Management Registers Auto-Neg Adv (Reg 4) Link Partner Ability Base (Reg 5) EMAC#CLIENTANINTERRUPT SGMII SGMII Link SGMII Capable BASE-T PHY SGMII Side BASE-T Side Auto-Neg Adv (Reg 4) Link Partner Ability Base (Reg 5) Auto-Neg Adv (Reg 4) Link Partner Ability Base (Reg 5) Figure 6-40: SGMII Auto-Negotiation Overview Copper Medium Link Partner Auto-Neg Adv (Reg 4) Link Partner Ability Base (Reg 5) PHY Link UG194_6_40_080409 The SGMII capable PHY has two distinctive sides to auto-negotiation as illustrated: The PHY initially performs auto-negotiation with its link partner across the PHY link using the relevant Auto-Negotiation standard for the chosen medium (BASE-T autonegotiation, illustrated in Figure 6-40, uses a copper medium). This resolves the operational speed and duplex mode with the link partner. The PHY then initiates a secondary Auto-Negotiation process with the Ethernet MAC across the SGMII link. This leverages the 1000BASE-X Auto-Negotiation specification described in “1000BASE-X Auto-Negotiation” with only minor differences. This transfers the results of the initial PHY with link partner auto-negotiation across the SGMII, and this is the only Auto-Negotiation process observed by the Ethernet MAC. The SGMII Auto-Negotiation function leverages the “1000BASE-X Auto-Negotiation” function with the exception of: The duration of the link timer of the SGMII auto-negotiation decreases from 10 ms to 1.6 ms making the entire Auto-Negotiation cycle faster (see “Auto-Negotiation Link Timer”). The information exchanged now contains speed resolution in addition to duplex mode. 196 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Serial Gigabit Media Independent Interface (SGMII) Under normal conditions, this completes the Auto-Negotiation information exchange. The results can be read from the “SGMII Auto-Negotiation Link Partner Ability Base Register (Register 5).” The duplex mode and speed of the Ethernet MAC should then be configured by a software routine to match. This does not happen automatically within the Ethernet MAC. There are two methods by which a host processor can learn of the completion of an Auto-Negotiation cycle: By polling the Auto-Negotiation completion bit 1.5 in “SGMII Status Register (Register 1),” page 132. By using the Auto-Negotiation interrupt port (see “Auto-Negotiation Interrupt,” page 197). Auto-Negotiation Link Timer The Auto-Negotiation Link Timer is used to time three phases of the Auto-Negotiation procedure. For the SGMII standard, this link timer is defined as having a duration of 1.6 ms. The duration of the link timer used by the Ethernet MAC can be configured with the EMAC#_LINKTIMERVAL[8:0] attribute (see “Physical Interface Attributes,” page 48). The duration of the timer is approximately equal to the binary value placed onto this attribute multiplied by 32.768 µs (4096 clock periods of the 125 MHz clock provided to the Ethernet MAC on PHYEMAC#GTXCLK). The accuracy of this link timer is within the range: +0 to -32.768 µs Therefore, for the SGMII standard, set the EMAC#_LINKTIMERVAL[8:0] attribute to: 000110010 = 50 decimal This corresponds to a timer duration of between 1.606 and 1.638 ms. This value can be reduced for simulation. Auto-Negotiation Interrupt The Auto-Negotiation function has an EMAC#CLIENTANINTERRUPT port. This port is designed to be used with common microprocessor bus architectures. The operation of this port is enabled or disabled and cleared via the “SGMII Vendor- Specific Register: Auto-Negotiation Interrupt Control Register (Register 16),” page 135. When disabled, this port is permanently driven Low. When enabled, this port is set to logic 1 following the completion of an Auto- Negotiation cycle. It remains High until cleared after a zero is written to bit 16.1 (Interrupt Status bit) of the “SGMII Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16).” Loopback When Using the PCS/PMA Sublayer Figure 6-41 illustrates the loopback options when using the PCS/PMA sublayer. Two possible loopback positions are illustrated: Loopback in the Ethernet MAC. When placed into loopback, data is routed from the transmitter to the receiver path at the last possible point in the PCS/PMA sublayer, immediately before the RocketIO serial transceiver interface. When placed into loopback, a constant stream of Idle code groups are transmitted through the RocketIO serial transceiver. TEMAC User Guide www.xilinx.com 197 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 149 and 150: R Gigabit Media Independent Interfa
Page 151 and 152: R Gigabit Media Independent Interfa
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217 and 218: R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220: R Clock Enables Modifications Relat
Page 221 and 222: R Additional Attributes Table C-2:
Page 223 and 224: R Appendix D Differences between So
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