Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 6: Physical Interface
PHYEMAC#MIITXCLK and PHYEMAC#RXCLK ports of the Ethernet MAC. It is also
used to clock both receiver and transmitter logic for the 16-bit Ethernet MAC client
interface and the RXUSRCLK and TXUSRCLK inputs of the GTX transceiver.
The global clock sourced from DCM CLKFX, running at 250 MHz, must be routed back to
the Ethernet MAC through the input ports CLIENTEMAC#RXCLIENTCLKIN and
CLIENTEMAC#TXCLIENTCLKIN. This clock is also connected to the
PHYEMAC#GTXCLK input of the Ethernet MAC and the RXUSRCLK2 and TXUSRCLK2
inputs of the transceiver.
The PLLLKDET signal from the RocketIO serial transceiver (indicating that its internal
PLLs have locked) is ANDed with the locked signal from the DCM and routed to the
CLIENTEMAC#DCMLOCKED input port of the Ethernet MAC. This ensures that the state
machines of the Ethernet MAC are held in reset until the RocketIO serial transceiver has
locked and all clocks are running cleanly.
As described in “Ethernet MAC Clock Generation,” page 206, the following clock signals
are unused and can be left unconnected:
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#PHYTXGMIIMIICLKOUT
EMAC#CLIENTTXCLIENTCLKOUT
1000BASE-X Auto-Negotiation
Overview of Operation
Figure 6-25 illustrates a simplified diagram of the Ethernet MAC instantiated within a
Virtex-5 device. The only components shown are two of the PCS Management Registers
that are directly involved in the Auto-Negotiation process (see “1000BASE-X PCS/PMA
Management Registers,” page 122). The corresponding registers of the connected device is
also shown.
Virtex-5 FPGA
Ethernet
MAC
Processor
Host Interface
PCS/PMA Management
Registers
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg 5)
EMAC#CLIENTANINTERRUPT
Figure 6-25: 1000BASE-X Auto-Negotiation Overview
174 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
Optical
Fibre
Link Partner
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg 5)
UG194_6_25_032508
R