Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 4: Host/DCR Bus Interfaces PLB v4.6 to DCR Bridge Processor System DCREMACENABLE Virtex-5 FPGA Figure 4-1 shows the internal structure of the host interface. The two Ethernet MACs within the same block share a single host interface. DCRHOSTDONEIR DCR Bus DCR Bridge Host Interface Ethernet MAC Block Host Bus 1 0 Figure 4-1: Host Interface EMAC1SEL EMAC1 EMAC0 1 0 UG194_4_01_071509 EMAC1SEL (internal signal) is driven by the HOSTEMAC1SEL input signal when using the host bus or decoded by the DCR bridge when using the DCR bus. The XPS_LL_TEMAC soft core delivered through the XPS tool controls the Ethernet MAC via the processor local bus (PLB) v4.6 interface. A bridge is provided to convert between the PLB v4.6 and DCR bus standards. For more information on the PLB v4.6 interface, see DS531, Processor Local Bus (PLB) v4.6 (v1.00a). 86 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPCODE[1:0] HOSTEMAC1SEL HOSTADDR[9:0] HOSTWRDATA[31:0] HOSTMIIMRDY HOSTRDDATA[31:0] DCREMACENABLE DCRHOSTDONEIR R Figure 4-2 shows the block diagram of the host interface. DCR Bus Ethernet MAC Block FPGA Logic Host Interface Figure 4-2: Ethernet MAC Host Interface Block Diagram Ethernet MAC Register Descriptions To access management registers in the PCS/PMA sublayer, the MDIO interface is used. The MDIO interface is described in detail in Chapter 5, “MDIO Interface,” and access to the MDIO through the host interface is discussed later in this chapter. Ethernet MAC Register Descriptions MIIMSEL0 REQ0 OPCODE0 ADDR0 WRD0 MIIMRDY0 RDD0 (All internal signals) MIIMSEL1 REQ1 OPCODE1 ADDR1 WRD1 MIIMRDY1 RDD1 EMAC0 EMAC1 UG194_4_02_0080409 Each Ethernet MAC has twelve configuration and address filter registers. These registers are accessed through the host interface and can be written to at any time. Both the receiver and transmitter logic only responds to configuration changes during Inter Frame gaps. The configurable resets are the only exception that take effect immediately. Writes made to address filter registers take effect immediately. To avoid corruption of incoming frames, writing to these registers should be made only while frame reception is not in progress. Table 4-1: Ethernet MAC Register Addresses Configuration and Address Filter Configuration and Address Filter PCS/ PMA0 Management Registers PCS/ PMA1 Management Registers TEMAC User Guide www.xilinx.com 87 UG194 (v1.10) February 14, 2011 MDIO MDIO ADDRESS[9:0] Register Description 0x200 Receiver Configuration (Word 0) 0x240 Receiver Configuration (Word 1) 0x280 Transmitter Configuration 0x2C0 Flow Control Configuration 0x300 Ethernet MAC Mode Configuration 0x320 RGMII/SGMII Configuration
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85: R Host/DCR Bus Interfaces This chap
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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