Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Appendix B: Ethernet MAC Clocks
TX
Client
Logic CE
RX CE
Client
Logic
GND
GND
Ethernet MAC Block
EMAC#CLIENTTXCLIENTCLKOUT
EMAC#CLIENTRXCLIENTCLKOUT
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
Figure B-3: Overview of Ethernet MAC Clock Connections to and from the FPGA Logic using Clock
Enables
Note: There are some complications in the use of the EMAC#CLIENTTXACK signal when using this
Clock Enable scheme. Refer to the specific physical interface section in Chapter 6 for details.
Transmitter Clock
Clock Generator
Output Clock Products
Input Clock Sources
TX
Client
Datapath
RX
Client
Datapath
TX
PHY
Datapath
RX
PHY
Datapath
EMAC#PHYTXGMIIMIICLKOUT
EMAC#PHYTXCLK
PHYEMAC#MIITXCLK
PHYEMAC#TXGMIIMIICLKIN
PHYEMAC#RXCLK
UG194_B_03_072206
EMAC#PHYTXGMIIMIICLKOUT can be placed onto global clock routing and used to clock
all of the transmitter physical logic. This resultant clock is then fed back into the Ethernet
MAC on the PHYEMAC#TXGMIIMIICLKIN, where it is used to derive the internal clock
used for the entire transmitter datapath (both physical and client). This has the effect of
eliminating clock skew between the Ethernet MAC and the FPGA logic (caused by the
global clock routing), enabling data to be reliably transferred between the two.
EMAC#CLIENTTXCLIENTCLKOUT is no longer used as a clock but instead as a clock
enable. Every flip-flop of the transmitter client logic can be clocked with the clock
connected to PHYEMAC#TXGMIIMIICLKIN, providing it has its clock enable connected as
illustrated. This configuration saves global clock resources when compared with the non
clock enable approach.
210 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
BUFG
NC
TX
PHY
Logic
TX Clock to PHY
RX
PHY
Logic
BUFG RX Clock from PHY
R