Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
GMII (Byte PHY) Mode
Clock Definitions and Frequencies
The clock signal input into PHYEMAC#RXCLK is sourced by the external PHY device at
1 Gb/s. At 10/100 Mb/s speeds, this clock should also originate from the external PHY
device but its frequency is divided by two in the FPGA logic (see “GMII Clock
Management for Tri-Speed Operation Using Byte PHY”). The resultant clock should be
used by the FPGA logic to clock the receiver client and physical interface logic. Internally
in the Ethernet MAC, this clock is used to derive all physical and client receiver clocks.
Table B-4: PHYEMAC#RXCLK Clock Frequencies
Clock Signal Direction
SGMII and 1000BASE-X PCS/PMA (8-Bit Data Client) Modes
This clock signal is unused and can be connected to logic 0.
1000BASE-X PCS/PMA (16-Bit Data Client) Mode
When operating in 1000BASE-X PCS/PMA (see “16-Bit Data Client”), this clock input
should be connected to a clock source that is half the frequency of the clock input into the
PHYEMAC#GTXCLK port.
EMAC#PHYTXGMIIMIICLKOUT, PHYEMAC#TXGMIIMIICLKIN
MII, GMII (non-Byte PHY), and RGMII Modes
EMAC#PHYTXGMIIMIICLKOUT is created by the clock generator to provide the frequencies
defined in Table B-5.
The clock signal input into the PHYEMAC#TXGMIIMIICLKIN port should be used to clock
the transmitter physical interface logic. This can be derived from
EMAC#PHYTXGMIIMIICLKOUT as illustrated in Figure B-2 and Figure B-3.
GMII (Byte PHY) Mode
Operating Speed
1000 Mb/s 100 Mb/s 10 Mb/s
PHYEMAC#RXCLK Input 125 MHz 12.5 MHz 1.25 MHz
Table B-5: EMAC#PHYTXGMIIMIICLKOUT, PHYEMAC#TXGMIIMIICLKIN Clock
Frequencies
Clock Signal Direction
Operating Speed
1000 Mb/s 100 Mb/s 10 Mb/s
EMAC#PHYTXGMIIMIICLKOUT Output 125 MHz 25 MHz 2.5 MHz
PHYEMAC#TXGMIIMIICLKIN Input 125 MHz 25 MHz 2.5 MHz
EMAC#PHYTXGMIIMIICLKOUT is created by the clock generator to provide the frequencies
defined in Table B-6. In Byte PHY mode, this should only be used at 1 Gb/s.
The clock signal input into PHYEMAC#TXGMIIMIICLKIN should be derived from
EMAC#PHYTXGMIIMIICLKOUT at 1 Gb/s. At 10/100 Mb/s speeds, this clock should
originate from the external PHY device but its frequency is divided by two in the FPGA
logic (see “GMII Clock Management for Tri-Speed Operation Using Byte PHY”). The
resultant clock should be used by the FPGA logic to clock the transmitter client and
TEMAC User Guide www.xilinx.com 213
UG194 (v1.10) February 14, 2011