Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 5: MDIO Interface To enable this functionality, the host interface should be disabled, and MDIO operation should be enabled (see Table 2-16, page 43). In this situation, an MDIO master external to the Ethernet MAC must initiate the “MDIO Transactions.” This MDIO master can exist in FPGA logic or as an external device. In this situation, the MDC clock must be provided to the Ethernet MAC through the PHYEMAC#MCKIN port. The output signal EMAC#PHYMCLKOUT should be left unconnected. The PCS/PMA Management registers have different definitions depending on the mode of operation. See as appropriate: “1000BASE-X PCS/PMA Management Registers” “SGMII Management Registers” 1000BASE-X PCS/PMA Management Registers FPGA PCS/PMA Sublayer MAC TX Interface MAC RX Interface MDIO Interface The PCS/PMA sublayer block, shown in Figure 5-7, is contained within the Ethernet MAC. The PCS/PMA sublayer contains PCS Management registers, as listed in Table 5-2. These registers are described in further detail in Table 5-3 through to Table 5-13. PCS Transmit Engine Auto-Negotiation PCS Receive Engine and Synchronization PCS Management Registers Figure 5-7: 1000BASE-X PCS/PMA Sublayer Logic and Physical Connections UG194_5_07_090809 Registers 0 through to 15, shown in Figure 5-7, are defined in IEEE Std 802.3. These contain information relating to the operation of the 1000BASE-X PCS/PMA sublayer, including the status of the physical Ethernet link (PHY link). Additionally, these registers are directly 122 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 GTP/GTX Transceiver TX+ TX- RX+ RX- GBIC or SFP Optical Transceiver PHY Link TX Optical Fiber RX R
R 1000BASE-X PCS/PMA Management Registers involved in the operation of the 1000BASE-X Auto-Negotiation function that occurs between the Ethernet MAC and its link partner, which is the Ethernet device connected at the far end of the PHY link (see “1000BASE-X Auto-Negotiation,” page 174). Registers 16 and 17 are vendor-specific registers, defined by Xilinx. Table 5-2: Configuration Registers for 1000BASE-X PCS/PMA Register Address Register Name (REGAD) 0 “Control Register (Register 0)” 1 “Status Register (Register 1)” 2,3 “PHY Identifier (Registers 2 and 3)” 4 “Auto-Negotiation Advertisement Register (Register 4)” 5 “Auto-Negotiation Link Partner Ability Base Register (Register 5)” 6 “Auto-Negotiation Expansion Register (Register 6)” 7 “Auto-Negotiation Next Page Transmit Register (Register 7)” 8 “Auto-Negotiation Next Page Receive Register (Register 8)” 15 “Extended Status Register (Register 15)” 16 Table 5-3: Control Register (Register 0) “Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)” 17 “Vendor-Specific Register: Loopback Control Register (Register 17)” Bit(s) Name Description Type Default Value 0.15 Reset 1 = PCS/PMA reset. 0 = Normal operation. 0.14 Loopback 1 = Enable loopback mode. 0 = Disable loopback mode. 0.13 Speed Selection (LSB) 0.12 Auto- Negotiation Enable The Ethernet MAC always returns a 0 for this bit. Along with bit 0.6, speed selection of 1000 Mb/s is identified. 1 = Enable Auto-Negotiation process. 0 = Disable Auto-Negotiation process. 0.11 Power Down 1 = Power down. 0 = Normal operation. When set to 1, the RocketIO serial transceiver is placed in a Low power state. This bit requires a reset (see bit 0.15) to clear. Read/Write Self Clearing EMAC#_PHYRESET “Physical Interface Attributes” Read/Write EMAC#_PHYLOOPBACKMSB “Physical Interface Attributes” Returns 0 0 Read/Write EMAC#_PHYINITAUTONEG_ENABLE “Physical Interface Attributes” Read/ Write EMAC#_PHYPOWERDOWN “Physical Interface Attributes” TEMAC User Guide www.xilinx.com 123 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121: Generic Host Bus DCR Bus R PHYEMAC#
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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