Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
RX Elastic Buffer Implementations
Selecting the Buffer Implementation from the GUI
Serial Gigabit Media Independent Interface (SGMII)
The GUI for the Ethernet MAC provides two options under the heading of SGMII
Capabilities. These options are:
Option 1: 10/100/1000 Mb/s clock tolerance compliant with Ethernet specification
For this option, if the FPGA and PHY clocks are independent and each has
100 ppm tolerance, an additional elastic buffer is required (100 slices and
1 block RAM per Ethernet MAC).
Option 2: 10/100/1000 Mb/s (restricted tolerance for clocks) OR 100/1000 Mb/s
For this option, if 10 Mb/s is not required OR it is required but the FPGA and
PHY clocks are closely related (see UG196, Virtex-5 RocketIO GTP Transceiver User
Guide or UG198, Virtex-5 RocketIO GTX Transceiver User Guide), the RX buffer can
be used (saves 100 slices and 1 block RAM per Ethernet MAC).
Option 1, the default mode, provides the implementation using the RX elastic buffer in the
FPGA logic. This alternative RX elastic buffer utilizes a single block RAM to create a buffer
that is twice as large as the one present in the RocketIO serial transceiver, therefore
consuming extra logic resources. However, this default mode provides reliable SGMII
operation.
Option 2 uses the RX elastic buffer in the RocketIO serial transceivers. This buffer, which is
half the size of the buffer in Option 1, can potentially underflow or overflow during SGMII
frame reception at 10 Mb/s operation (see “The FPGA RX Elastic Buffer Requirement”).
However, in logical implementations where this case is proven reliable, this option is
preferred because of its lower logic utilization.
The FPGA RX Elastic Buffer Requirement
Figure 6-29 illustrates a simplified diagram of a common situation where the
Ethernet MAC in SGMII mode is interfaced to an external PHY device. Separate oscillator
sources are used for the FPGA and the external PHY. The Ethernet specification uses clock
sources with a 100 ppm tolerance. In Figure 6-29, the clock source for the PHY is slightly
faster than the clock source to the FPGA. Therefore, during frame reception, the RX elastic
buffer (implemented in the RocketIO serial transceiver in this example) starts to fill up.
Following frame reception in the interframe gap period, idles are removed from the
received datastream to return the RX elastic buffer to half-full occupancy. This task is
performed by the clock correction circuitry (see UG196, Virtex-5 RocketIO GTP Transceiver
User Guide or UG198, Virtex-5 RocketIO GTX Transceiver User Guide).
TEMAC User Guide www.xilinx.com 181
UG194 (v1.10) February 14, 2011