Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 3: Client Interface
PHYEMAC#TXGMIIMIICLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
EMAC#CLIENTTXACK (Registered)
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
Figure 3-10: Normal Frame Transmission at 10/100 Mb/s with EMAC#_USECLKEN Set to TRUE
Transmit (TX) Client: 16-Bit Interface
DA SA L/T DATA
UG194_3_10_072206
This optional configuration can only be used when the Ethernet MAC physical interface is
configured in 1000BASE-X PCS/PMA mode.
When a 16-bit client interface is selected, the input clock for the Ethernet MAC TX client
logic (CLIENTEMAC#TXCLIENTCLKIN) should be twice the frequency of the clock used for
the TX client logic in the FPGA logic. Figure 6-22, page 170 illustrates how this clocking
scheme is achieved for this mode of operation.
This mode can operate with the Ethernet MAC TX client logic clocked at 125 MHz and the
logic in the FPGA logic clocked at 62.5 MHz. However, this mode allows the Ethernet
MAC TX client logic to operate at up to 250 MHz while the logic in the FPGA logic is
clocked at 125 MHz. By using the faster clock speeds, a line rate of up to 2.5 Gb/s can be
achieved. This is greater than 1 Gb/s, as specified in IEEE Std 802.3. Therefore, this
interface should not be used for Ethernet compliant designs, but it can be useful for
backplane applications.
“Ethernet MAC Attributes,” page 42 describes the EMAC#_TX16BITCLIENT_ENABLE
attribute, which is set to TRUE for this configuration.
Figure 3-11 shows the timing of a normal outbound frame transfer for the case with an
even number of bytes in the frame. The CLIENTEMAC#TXCLIENTCLKIN clock is used as an
input to the Ethernet MAC and the PHYEMAC#MIITXCLK clock
(CLIENTEMAC#TXCLIENTCLKIN/2) is used to clock the TX client logic in the FPGA logic.
60 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
R