Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Appendix B: Ethernet MAC Clocks
Ethernet MAC Clock Generation
As shown in Figure B-1, included in the Ethernet MAC is a Clock Generator module. This
module is provided with input clock sources, from which the following output clock
products are generated:
EMAC#PHYTXGMIIMIICLKOUT
EMAC#PHYTXCLK
EMAC#CLIENTTXCLIENTCLKOUT
EMAC#CLIENTRXCLIENTCLKOUT
For these generated output clocks (refer to “Clock Definitions and Frequencies”):
the output clocks are always at the correct frequency for their associated interfaces for
any mode of operation and switch frequencies cleanly during speed changes
the output clocks are NOT used internally by any Ethernet MAC logic
the output clocks are provided only for the convenience of the user; they do not have
to be used by the FPGA logic
Ethernet MAC Input Clocks
As shown in Figure B-1, the following clock signals are input into the Ethernet MAC clock
generator:
PHYEMAC#GTXCLK
PHYEMAC#MIITXCLK
PHYEMAC#RXCLK
PHYEMAC#TXGMIIMIICLKIN
CLIENTEMAC#RXCLIENTCLKIN
CLIENTEMAC#TXCLIENTCLKIN
Not all clock input sources are required in all modes. Required clock input signals must
always be driven by the FPGA logic at the correct frequency for the required mode of
operation (see “Clock Definitions and Frequencies”).
Only the input clocks are collectively responsible for the correct operation of the Ethernet
MAC. It is possible to ignore all clock generator output clocks for correct Ethernet MAC
operation, providing the input clocks are alternatively derived. However, the clock
generator output clocks are provided precisely for this purpose.
Clock Connections to and from FPGA Logic
The clock logic described here is not optimized for specific user modes. There are cases
where two or more clock generator input clocks can be shared from a common source. This
can be a common client clock, shared between transmitter and receiver; in other cases, this
can be a common transmitter clock shared between both client and physical domains. It is
also possible to share common clocks between two of more Ethernet MACs. Chapter 6,
“Physical Interface,” provides clock management information for optimal clock logic
efficiency based on the chosen physical interfaces.
This section provides general-purpose clock logic descriptions to aid in the understanding
of the Ethernet MAC, and clock sharing is not considered. Three main clocking modes are
to be discussed:
206 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
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