Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 4: Host/DCR Bus Interfaces Before exiting the interrupt service routine, the host should write to this register to clear the interrupt request bit. To read and clear the IRSTATUS_e# register, the following operations must be performed on the DCR bus: 1. To access the IRSTATUS_e# register, write an address code of 0x3A0 to the cntlReg register, addressing cntlReg using EMAC0_DCRBASEADDR for IRSTATUS_e0, and EMAC1_DCRBASEADDR for IRSTATUS_e1. The write enable bit should be cleared to indicate a read. 2. The register information for IRSTATUS_e# is loaded into dataRegLSW. Read this register to access the data. 3. To clear the interrupt, the contents of the IRSTATUS_e# register should be written to zero. Write a value of all zeros into the dataRegLSW. 4. Write the cntlReg with the address 0x3A0 to load the data from dataRegLSW into the register IRSTATUS_e# and clear the interrupt. The write enable bit should be set to 1 to indicate a write. To read from the EMAC0 IRSTATUS_e0 register and then clear the register: // Write the address of IRStatus_e0 register 0x3A0 to the // cntlReg_e0 register. Ensure that the write enable bit is not asserted dcr_write(EMAC0_DCRBASEADDR + 2, 0x000003A0); // Read the IRSTATUS_e0 data from the dataRegLSW dcr_read (EMAC0_DCRBASEADDR + 1); // Write a value of all zeros to the dataRegLSW dcr_write(EMAC0_DCRBASEADDR + 1, 0x00000000); // Write to the cntlReg_e0 register to load the data into the // IRStatus_e0 register to clear the interrupt dcr_write(EMAC0_DCRBASEADDR + 2, 0x000083A0); The IRENABLE_e# register is programmed to enable the different interrupt types to trigger the DCRHOSTDONEIR interrupt. When an enable bit is set, the corresponding bit in the IRSTATUS_e# register is updated when an interrupt of that type occurs. To read from this register and then write back, the following steps are required. 1. To read the IRENABLE_e# register, write an address code 0x3A4 to the cntlReg, addressing the cntlReg using EMAC0_DCRBASEADDR for IRENABLE_e0, and EMAC1_DCRBASEADDR for IRENABLE_e1, the write enable bit should be cleared to indicate a read operation. 2. The register information for IRENABLE_e# is loaded into the dataRegLSW register. Read this register to access the data. 3. To enable specific interrupts, write the required bitmask value to the dataRegLSW register. 4. Write to the cntlReg with the address code 0x3A4 to load the data from datRegLSW into the IRENABLE_e# register. The write enable bit should be set to 1 to indicate a write operation. To read from the EMAC1 IRENABLE_e1 register and then enable all interrupts: // Write the address of IRENABLE_e1 register 0x3A4 to the // cntlReg_e1 register. Ensure that the write enable bit is not asserted dcr_write(EMAC1_DCRBASEADDR + 2, 0x000003A4); // Read the IRENABLE_e1 data from the dataRegLSW dcr_read (EMAC1_DCRBASEADDR + 1); // Write a value of all ones to the dataRegLSW dcr_write(EMAC1_DCRBASEADDR + 1, 0x0000007F); 108 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R // Write to the cntlReg_e1 register to load the data into the // IRENABLE_e1 register and enable all interrupts dcr_write(EMAC1_DCRBASEADDR + 2, 0x000083A4); Ethernet MAC Configuration and Address Filter Access Reading from an Ethernet MAC Configuration Register Using the DCR Bus To read from an Ethernet MAC configuration register, the user must perform the following sequence of operations on the DCR bus: 1. To access EMAC0, use EMAC0_DCRBASEADDR. To access EMAC1, use EMAC1_DCRBASEADDR. Write to the cntlReg register, with the write enable bit cleared to 0, to indicate a read operation and set the address code to the desired address of the Ethernet MAC configuration register to be accessed. The address code maps directly to the Ethernet MAC address codes given in Table 4-1. 2. Poll the RDYstatus_e# register until the configuration Read-Ready bit is set to 1 or wait until the DCRHOSTDONEIR interrupt is asserted. 3. Read from the dataRegLSW register to access data from the Ethernet MAC configuration register. The following code demonstrates a processor routine to read from an Ethernet MAC configuration register. To read from the EMAC0 transmitter configuration register: // EMAC Configuration Register 0x280 (EMAC0 Transmitter Configuration) // Write the address of EMAC0 Transmitter Configuration register to the // cntlReg_e0 register dcr_write(EMAC0_DCRBASEADDR + 2, 0x00000280); // Poll the RDYstatus_e0 register while ( !(dcr_read(EMAC0_DCRBASEADDR + 3) & 0x00010000) ); // Read the dataRegLSW with the values returned from the EMAC0 // Transmitter Configuration register dcr_read (EMAC0_DCRBASEADDR + 1); Writing to an Ethernet MAC Configuration Register To write to an Ethernet MAC configuration register, the user must perform the following sequence of operations on the DCR bus: 1. Write to the dataRegLSW register with the desired value for the Ethernet MAC configuration register. This value is mapped to the host configuration register. 2. Write to the cntlReg register with the desired address of the Ethernet MAC configuration register and the write enable bit to logic 1. Use EMAC0_DCRBASEADDR to access EMAC0 and EMAC1_DCRBASEADDR to access EMAC1. 3. Poll the RDYstatus_e# register until the configuration Write-Ready bit is set to 1 or wait until the DCRHOSTDONEIR interrupt is asserted. To write to the EMAC1 flow control register: // EMAC Configuration Register 0x2C0 (EMAC Flow Control) // Write to enable the flow control on both the transmit and receive // side of EMAC1, set bits 29 and 30 to 1 dcr_write(EMAC1_DCRBASEADDR + 1, 0x60000000); // Write the address of Flow Control register to the cntlReg_e1 // register, with the write enable bit asserted dcr_write(EMAC1_DCRBASEADDR + 2, 0x000082C0); TEMAC User Guide www.xilinx.com 109 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107: R Using the DCR Bus The IRENABLE_e#
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 155 and 156: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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R Reduced Gigabit Media Independent
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R Reduced Gigabit Media Independent
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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