Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
Clock Enables
Clock Connections to and from FPGA Logic
For GMII transmitter operation at 1 Gb/s, both client and physical interfaces have an 8-bit
datapath operating at 125 MHz. If 1 Gb/s is the only speed of interest, a single clock
domain can be used for both client and physical interfaces.
For MII transmitter operation at 100 Mb/s, the client interface still has an 8-bit datapath
that operates at 12.5 MHz. However, the physical interface width dropped to 4 bits and is,
therefore, clocked at twice the frequency of the client (25 MHz).
The Clock Enable approach always clocks the client interface with the physical interface
clock, while also providing the client with a clock enable. At 1 Gb/s, the physical interface
clock is 125 MHz, which is also required by the client; the clock enable is constantly held
High. At 100 Mb/s, the physical interface clock is 25 MHz, which is twice that required by
the client. The clock enable toggles on alternative 25 MHz clock cycles to enable the client
logic at the resultant rate of 12.5 MHz.
This methodology is applied similarly to the receiver path. GMII/MII and RGMII physical
interfaces can all use this clocking scheme at all three Ethernet speeds.
Figure B-3 shows clock logic instantiated in the FPGA logic when using the clock enables.
Refer to “Clock Definitions and Frequencies,” page 211 for relationships between clocks
and clock enables). Figure B-3 and the text that follows describe how the clock signals
required to use the Ethernet MAC can be derived from the output clocks (and clock
enables) from the Ethernet MACs clock generator.
TEMAC User Guide www.xilinx.com 209
UG194 (v1.10) February 14, 2011