Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Date Version Revision 04/28/09 1.8 All chapters: Changed references to FXT devices to include both TXT and FXT devices. Replaced the term platform with the term device. Replaced the term SmartModel with the term SecureIP model. Chapter 2: Changed references to GTP transceiver to GTP/GTX transceiver in Figure 2-1, page 27, Figure 2-2, page 29, and Figure 2-3, page 32. Chapter 3: Revised the text of “Client-Supplied FCS Passing” on page 53. Chapter 5: Changed references to GTP transceiver to GTP/GTX transceiver in Figure 5-4, page 119, Figure 5-6, page 121, Figure 5-7, page 122, and Figure 5-8, page 130. Chapter 6: Revised Note 1 to indicate the clock input of IFD can be driven by a BUFIO in Figure 6-3, page 141, Figure 6-8, page 148, Figure 6-14, page 157, and Figure 6-15, page 159. Added Note 1 indicating a BUFG buffer can be replaced by a BUFR and the clock input of IFD can be driven by a BUFIO in Figure 6-4, page 142, Figure 6-6, page 145, Figure 6-7, page 147, and Figure 6-10, page 152. Added Note 1 indicating a BUFG buffer can be replaced by a BUFR and the clock input of IDDR can be driven by a BUFIO in Figure 6-12, page 154, Figure 6-13, page 156, Figure 6-16, page 160, and Figure 6-17, page 162. Where a RocketIO® transceiver is shown, added the term RocketIO in Figure 6-21, page 169, Figure 6-22, page 170, Figure 6-36, page 191, and Figure 6-37, page 192. Revised schematic by adding a BUFGMUX to the PHYEMAC#MIITXCLK input in Figure 6-8, page 148. Revised schematic by changing the I0 input source for the BUFGMUX on the PHYEMAC#TXGMIIMIICLKIN input in Figure 6-8, page 148. Revised schematic by adding a BUFG buffer between the transceiver REFCLKOUT output and the DCM CLKIN input in Figure 6-22, page 170, Figure 6-23, page 172, Figure 6-24, page 173, Figure 6-38, page 194, and Figure 6-39, page 195. Changed references to GTP transceiver to GTP/GTX transceiver in Figure 6-28, page 179, Figure 6-29, page 182, Figure 6-33, page 186, and Figure 6-41, page 198. Added link to UG198 in “RX Elastic Buffer Implementations” on page 181 and “The FPGA RX Elastic Buffer Requirement” on page 181. TEMAC User Guide www.xilinx.com UG194 (v1.10) February 14, 2011
Date Version Revision 10/01/09 1.9 Chapter 1: Revised first paragraph in “Frame Transmission and Interframe Gap,” page 23. Chapter 2: Revised EMAC#_RXFLOWCTRL_ENABLE and EMAC#_TXFLOWCTRL_ENABLE descriptions in Table 2-17, page 45. Chapter 3: Revised first paragraph in “Flow Control Block,” page 73. Chapter 5: Revised Link Status description in Table 5-4, page 124. 02/14/11 1.10 Updated description of EMAC#_PAUSEADDR[47:0] in Table 2-17. Added description of standard and alternative clock management to “Transmitter Statistics Vector” and “Receiver Statistics Vector.” Updated Table 4-14. Added “Use of Clock Correction Sequences.” UG194 (v1.10) February 14, 2011 www.xilinx.com TEMAC User Guide
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3: Date Version Revision 08/08/07 (con
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56:
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58:
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60:
R Normal Frame Transmission PHYEMAC
Page 61 and 62:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66:
R Frame Reception with Errors CLIEN
Page 67 and 68:
R Receive (RX) Client: 8-Bit Interf
Page 69 and 70:
R Receive (RX) Client: 16-Bit Inter
Page 71 and 72:
R Address Filtering Address Filteri
Page 73 and 74:
R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76:
R Transmitting a PAUSE Control Fram
Page 77 and 78:
R Operation Figure 3-30 illustrates
Page 79 and 80:
R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82:
R Table 3-3: Bit Definitions for th
Page 83 and 84:
R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86:
R Host/DCR Bus Interfaces This chap
Page 87 and 88:
HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90:
R Table 4-3: Receiver Configuration
Page 91 and 92:
R Table 4-5: Flow Control Configura
Page 93 and 94:
R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96:
R Table 4-9: Unicast Address (Word
Page 97 and 98:
R Table 4-13: Address Filter Mode 0
Page 99 and 100:
R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102:
R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104:
R Using the DCR Bus The directly ad
Page 105 and 106:
R Table 4-18: DCR Control Register
Page 107 and 108:
R Using the DCR Bus The IRENABLE_e#
Page 109 and 110:
R // Write to the cntlReg_e1 regist
Page 111 and 112:
DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114:
R Using the DCR Bus // EMAC Managem
Page 115 and 116:
R MDIO Interface Chapter 5 This cha
Page 117 and 118:
MDC MDIO R MDIO Transactions Introd
Page 119 and 120:
R MDIO Implementation in the Ethern
Page 121 and 122:
Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124:
R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126:
R Table 5-4: Status Register (Regis
Page 127 and 128:
R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130:
R Table 5-13: Vendor-Specific Regis
Page 131 and 132:
R 2, 3 “PHY Identifier (Registers
Page 133 and 134:
1.2 SGMII Link Status R Table 5-16:
Page 135 and 136:
R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138:
R Physical Interface Chapter 6 This
Page 139 and 140:
R GMII / MII RGMII SGMII Introducti
Page 141 and 142:
TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144:
R Gigabit Media Independent Interfa
Page 145 and 146:
GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148:
GTX_CLK R IBUFG BUFG TX Client Logi
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
R Reduced Gigabit Media Independent
Page 155 and 156:
Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
Page 159 and 160:
GTX_CLK TX Client Logic RX Client L
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168:
R Ethernet MAC to RocketIO Serial T
Page 169 and 170:
TX and RX Client Logic R 1000BASE-X
Page 171 and 172:
R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174:
R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176:
R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180:
FPGA R Introduction to the SGMII Im
Page 181 and 182:
R RX Elastic Buffer Implementations
Page 183 and 184:
R Serial Gigabit Media Independent
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192:
TX and RX Client Logic R SGMII Cloc
Page 193 and 194:
Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 197 and 198:
Page 199 and 200:
R Interfacing to a Statistics Block
Page 201 and 202:
R Using the DCR Bus to Access Stati
Page 203 and 204:
R Pinout Guidelines Appendix A Xili
Page 205 and 206:
R Ethernet MAC Clocks Appendix B Th
Page 207 and 208:
TX Client Logic RX Client Logic R
Page 209 and 210:
R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
Page 213 and 214:
R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216:
R Clock Definitions and Frequencies
Page 217 and 218:
R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220:
R Clock Enables Modifications Relat
Page 221 and 222:
R Additional Attributes Table C-2:
Page 223 and 224:
R Appendix D Differences between So
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