Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface Shim Because of differences in the way the Virtex-II Pro and Virtex-4 FPGA RocketIO transceivers and the Virtex-5 FPGA RocketIO serial transceivers output the undecoded 8B/10B code group when RXNOTINTABLE is asserted, a shim is needed. This shim modifies the received data from the Virtex-5 FPGA RocketIO serial transceiver to the format that the Ethernet MAC is expecting. Table 6-4 describes the functionality of this shim. The shim created by the CORE Generator tool is combinatorial. If this logic is pipelined, all of the signals originating from the RocketIO serial transceiver highlighted with gray shading in Figure 6-34 must be pipelined with an equal latency. Table 6-4: Shim Functionality Connection to RocketIO Serial Transceiver Port Name Ethernet MAC Port Name When RXNOTINTABLE#[0] = 0 When RXNOTINTABLE#[0] = 1 PHYEMAC#RXD[7] PHYEMAC#RXD[6] PHYEMAC#RXD[5] PHYEMAC#RXD[4] PHYEMAC#RXD[3] PHYEMAC#RXD[2] PHYEMAC#RXD[1] PHYEMAC#RXD[0] RXDATA#[7] RXDATA#[6] RXDATA#[5] RXDATA#[4] RXDATA#[3] RXDATA#[2] RXDATA#[1] RXDATA#[0] RXDATA#[2] RXDATA#[3] RXDATA#[4] RXDATA#[5] RXDATA#[6] RXDATA#[7] RXCHARISK#[0] RXDISPERR#[0] PHYEMAC#RXRUNDISP RXRUNDISP#[0] RXDATA#[1] PHYEMAC#RXCHARISK RXCHARISK#[0] RXDATA#[0] 190 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
TX and RX Client Logic R SGMII Clock Management (LXT and SXT Devices) BUFG X Tri-Speed Operation Serial Gigabit Media Independent Interface (SGMII) Figure 6-36 shows the clock management used with the SGMII interface without the FPGA logic elastic buffer. The CLKIN inputs to the RocketIO serial transceiver must be connected to an external, high-quality differential reference clock of frequency of 125 MHz. A 125 MHz clock source is then provided to the FPGA logic from the REFCLKOUT output port of the RocketIO serial transceiver. This is connected to global clock routing using a BUFG as illustrated (Figure 6-36). This clock should then be routed to the PHYEMAC#GTXCLK of the Ethernet MAC. PHYEMAC#GTXCLK Ethernet MAC PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXCLIENTCLKIN EMAC#CLIENTTXCLIENTCLKOUT CLIENTEMAC#RXCLIENTCLKIN PHYEMAC#MIITXCLK EMAC#CLIENTRXCLIENTCLKOUT CLIENTEMAC#DCMLOCKED PHYEMAC#RXCLK 125 MHz RocketIO GTP Transceiver PLLLKDET TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 6-36: SGMII Clock Management - RocketIO Serial Transceiver RX Elastic Buffer In bypassing the RocketIO serial transceiver RX elastic buffer, data is clocked out of the RocketIO serial transceiver synchronously to RXRECCLK. This clock, placed on a BUFR component, drives RXUSRCLK and RXUSRCLK2 and some of the logic in the RX elastic buffer as illustrated in Figure 6-37. TEMAC User Guide www.xilinx.com 191 UG194 (v1.10) February 14, 2011 X BUFG IBUFDS CLKIN REFCLKOUT UG194_6_36_080409
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189: R Ethernet MAC (PCS/PMA Sublayer) E
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217 and 218: R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220: R Clock Enables Modifications Relat
Page 221 and 222: R Additional Attributes Table C-2:
Page 223 and 224: R Appendix D Differences between So
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