Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
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GTX_CLK<br />
R<br />
IBUFG<br />
TX CLIENT<br />
LOGIC<br />
RX CLIENT<br />
LOGIC<br />
BUFG<br />
x<br />
x<br />
E<strong>MAC</strong>#<br />
PHYE<strong>MAC</strong>#GTXCLK<br />
PHYE<strong>MAC</strong>#TXGMIIMIICLKIN<br />
E<strong>MAC</strong>#PHYTXGMIIMIICLKOUT<br />
CLIENTE<strong>MAC</strong>#TXCLIENTCLKIN<br />
E<strong>MAC</strong>#CLIENTTXCLIENTCLKOUT<br />
E<strong>MAC</strong>#PHYTXD[7:0]<br />
PHYE<strong>MAC</strong>#MIITXCLK<br />
CLIENTE<strong>MAC</strong>#RXCLIENTCLKIN<br />
E<strong>MAC</strong>#CLIENTRXCLIENTCLKOUT<br />
PHYE<strong>MAC</strong>#RXCLK<br />
PHYE<strong>MAC</strong>#RXD[7:0]<br />
CLIENTE<strong>MAC</strong>#DCMLOCKED<br />
Notes:<br />
1) A regional buffer (BUFR) can replace this BUFG.<br />
In addition, the clock input of IFD can be driven by a BUFIO.<br />
Refer to UG190, <strong>Virtex</strong>-5 <strong>FPGA</strong> User Guide for BUFR usage guidelines.<br />
Figure 6-6: 1 Gb/s GMII Clock Management<br />
Gigabit Media Independent Interface (GMII)<br />
GTX_CLK must be provided to the <strong>Ethernet</strong> <strong>MAC</strong>. This high-quality, 125 MHz clock<br />
satisfies the IEEE Std 802.3-2002 requirements.<br />
The GTX_CLK input is routed onto the global clock network via an IBUFG and BUFG. The<br />
output of the BUFG connects to:<br />
GMII_TXD registers in the <strong>FPGA</strong> logic<br />
PHYE<strong>MAC</strong>#TXGMIIMIICLKIN input port<br />
CLIENTE<strong>MAC</strong>#TXCLIENTCLKIN<br />
TX client logic<br />
GMII_TX_CLK is forwarded along with the GMII data signals from the <strong>FPGA</strong> to the PHY.<br />
An IOB DDR output register is used; this is a predictable way to produce the clock because<br />
the clock-to-pad delay is the same as that for the GMII_TXD signals. This forwarded clock<br />
TE<strong>MAC</strong> User Guide www.xilinx.com 145<br />
<strong>UG194</strong> (v1.10) February 14, 2011<br />
x<br />
0<br />
1<br />
BUFG (1)<br />
IFD<br />
Q D<br />
D<br />
OFD<br />
Q<br />
ODDR<br />
D1<br />
D2<br />
IDELAY<br />
IDELAY<br />
OBUF<br />
OBUF<br />
IBUFG<br />
IBUF<br />
GMII_TXD[7:0]<br />
GMII_TX_CLK<br />
GMII_RX_CLK<br />
GMII_RXD[7:0]<br />
<strong>UG194</strong>_6_06_091409