Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 6: Physical Interface
+0 to -32.768 µs
Therefore, for the 1000BASE-X standard, the attribute EMAC#_LINKTIMERVAL[8:0] is set
to:
100111101 = 317 decimal
This setting corresponds to a timer duration of between 10.354 and 10.387 ms. This value
can be reduced for simulation.
Auto-Negotiation Interrupt
The Auto-Negotiation function has an EMAC#CLIENTANINTERRUPT port. This port is
designed to be used with common microprocessor bus architectures.
The operation of this port is enabled or disabled and cleared via the “Vendor-Specific
Register: Auto-Negotiation Interrupt Control Register (Register 16).”
When disabled, this port is permanently driven Low.
When enabled, this port is set to logic 1 following the completion of an Auto-
Negotiation cycle. It remains High until cleared after a zero is written to bit 16.1
(Interrupt Status bit) of the “Vendor-Specific Register: Auto-Negotiation Interrupt
Control Register (Register 16).”
Use of Clock Correction Sequences
The RocketIO serial transceiver is configured by the appropriate Transceiver Wizard to
perform clock correction. The output of the Transceiver Wizard is provided as part of the
Ethernet MAC wrapper generated using the CORE Generator tool. Two different clock
correction sequences can be employed:
The mandatory clock correction sequence is the /I2/ ordered set; this is a two-byte
code-group sequence formed from /K28.5/ and /D16.2/ characters. The /I2/
ordered set is present in the interframe gap. These sequences can therefore be
removed or inserted by the transceiver’s receiver elastic buffer without causing frame
corruption.
The default Transceiver Wizard configuration enables the CLK_COR_SEQ_2_USE
attribute. In this case, the transceiver is also configured to perform clock correction on
the /K28.5/D21.5/ sequence; these are the first two code-groups from the /C1/
ordered set (the /C1/ ordered set is four code-groups in length). Because there are no
/I2/ ordered sets present during much of the auto-negotiation cycle, this provides a
method of allowing clock correction to be performed during auto-negotiation.
Because this form of clock correction inserts or removes two code groups into or from
a four code-group sequence, this causes ordered-set fragments to be seen by the
Ethernet MAC’s auto-negotiation state machine. It is therefore important that the
transceiver’s RXCLKCORCNT[2:0] port be correctly connected to the Ethernet MAC;
this indicates a clock correction event (and type) to the Ethernet MAC. Using this
signal, the Ethernet MAC’s state machine can interpret the clock-correction fragments,
and the auto-negotiation function can complete cleanly.
When the transceiver’s CLK_COR_SEQ_2_USE attribute is not enabled, no clock
correction can be performed during much of the auto-negotiation cycle. When this is
the case, it is possible that the transceiver’s receiver elastic buffer could underflow or
overflow as asynchronous clock tolerances accumulate. This results in an elastic buffer
error. It is therefore important that the transceiver’s RXBUFSTATUS[2:0]port is
correctly connected to the Ethernet MAC; this indicates a buffer error event to the
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UG194 (v1.10) February 14, 2011
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