Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface IBUFG BUFGMUX MII_TX_CLK I1 GTX_CLK TX Client Logic RX Client Logic CE ACK CE IBUFG I0 I1 I0 FDE Q D EMAC# PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT PHYEMAC#GTXCLK EMAC#PHYTXD[7:0] PHYEMAC#MIITXCLK EMAC#CLIENTTXCLIENTCLKOUT EMAC#CLIENTTXACK EMAC#SPEEEDIS10100 CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#RXCLIENTCLKIN PHYEMAC#RXCLK EMAC#CLIENTRXCLIENTCLKOUT EMAC#PHYRXD[7:0] Notes: 1) A regional buffer (BUFR) can replace this BUFG. In addition, the clock input of IFD can be driven by a BUFIO. Refer to UG190, Virtex-5 FPGA User Guide for BUFR usage guidelines. Figure 6-10: Tri-Mode GMII Clock Management with Clock Enable GMII_TX_CLK GMII_RX_CLK UG194_6_10_080409 At 1 Gb/s, all external logic is clocked at 125 MHz. At 100 Mb/s and 10 Mb/s, the logic is clocked at 25 MHz and 2.5 MHz, respectively. To maintain the correct data rate at the client, interface clock enable signals are output on EMAC#CLIENTTXCLIENTCLKOUT for the transmitter logic and on EMAC#CLIENTRXCLIENTCLKOUT for the receiver logic. These signals are High during 1 Gb/s operation and toggle on each clock edge at slower speeds. These are used to enable the client interface logic. Due to the timing relationship between the GMII transmit clock and the internal client clock signals, the TX_ACK signal (CLIENTEMAC#TXACK) is registered at the output of the Ethernet MAC when operating at speeds below 1 Gb/s. At 1 G b/s, the register is bypassed. The GMII_TX_CLK is derived from the GTX_CLK input when the MAC is operating at 1 Gb/s and from the MII_TX_CLK input when the MAC is operating at a lower speed. It is 152 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 X 0 1 ODDR D1 Q D2 OFD BUFG (1) IFD OBUF OBUF D Q GMII_TXD[7:0] IDELAY Q D IDELAY IBUFG IBUF GMII_RXD[7:0] R
R Reduced Gigabit Media Independent Interface (RGMII) routed through an OBUF and then connected to the PHY. Its frequency changes between 125 MHz, 25 MHz, or 2.5 MHz depending on the speed setting of the Ethernet MAC. This clocking scheme requires two fewer BUFGs than the default scheme detailed in Figure 6-8. Reduced Gigabit Media Independent Interface (RGMII) Reduced GMII (RGMII), defined by Hewlett-Packard, is an alternative to GMII. It reduces the number of pins required to connect the Ethernet MAC to the PHY from 24 to 12, when compared with GMII. RGMII achieves this 50% pin count reduction in the interface by using DDR flip-flops. For this reason, RGMII is preferred over GMII by PCB designers. RGMII can carry Ethernet traffic at 10 Mb/s, 100 Mb/s, and 1 Gb/s. For more information on RGMII, refer to the Hewlett-Packard RGMII Specification, version 1.3 and 2.0. Figure 6-11 shows the Ethernet MAC configured for RGMII. The physical signals of the Ethernet MAC are connected through IOBs to the external interface. The “logic cloud” indicates that alternative implementations are possible. Ethernet MAC IOBs and Clock Logic Virtex-5 FPGA RGMII_RXC RGMII_RXD[3:0] RGMII_RX_CTL RGMII_TXC RGMII_TXD[3:0] RGMII_TX_CTL GTX_CLK Figure 6-11: Ethernet MAC Configured in RGMII Mode There are several implementations for both RGMII v1.3 and v2.0, which use alternative clocking schemes. “Ethernet MAC Clocks,” page 205 introduces these clocking models. They are described in detail in the following sections: “RGMII Clock Management for 1 Gb/s Only” At 1 Gb/s speeds only, client interface and physical interface clocks always run at the same frequency (125 MHz). This enables efficient clock logic implementations. “RGMII Standard Clock Management for Tri-Speed Operation” The standard clocking scheme for tri-speed operation. “RGMII Clock Management for Tri-Speed Operation Using Clock Enables” An advanced clocking scheme for tri-speed operation that saves global clock resources. TEMAC User Guide www.xilinx.com 153 UG194 (v1.10) February 14, 2011 RGMII Physical Interface UG194_6_11_0080409
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 149 and 150: R Gigabit Media Independent Interfa
Page 151: R Gigabit Media Independent Interfa
Page 155 and 156: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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