Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

More documents

Recommendations

Info

Chapter 6: Physical Interface TX Client Logic CE ACK RX Client Logic CE RGMII Version 2.0 GTX_CLK I0 I1 Figure 6-17 shows the clock management scheme for tri-speed RGMII v2.0 operation when the EMAC#_USECLKEN attribute is set. Q D CE IBUF PHYEMAC#GTXCLK EMAC# PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT EMAC#CLIENTTXCLIENTCLKOUT CLIENTEMAC#TXCLIENTCLKIN EMAC#PHYTXD[3:0] EMAC#CLIENTTXACK EMAC#PHYTXD[7:4] EMAC#SPEEDIS10100 PHYEMAC#MIITXCLK CLIENTEMAC#RXCLIENTCLKIN PHYEMAC#RXCLK EMAC#CLIENTRXCLIENTCLKOUT CLIENTEMAC#DCMLOCKED Notes: 1) A regional buffer (BUFR) can replace this BUFG. In addition, the clock input of IDDR can be driven by a BUFIO. Refer to UG190, Virtex-5 FPGA User Guide for BUFR usage guidelines. PHYEMAC#RXD[3:0] PHYEMAC#RXD[7:4] Figure 6-17: Tri-Mode RGMII with Clock Enables In this mode of operation, the transmitter signals are synchronous to PHYEMAC#TXGMIIMIICLKIN, and the receiver signals are synchronous to PHYEMAC#RXCLK. 162 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 1 0 BUFG D1 D2 ODDR Q OBUF BUFG (1) IBUFG IDELAY RGMII_TXD[3:0] RGMII_RXC IDDR Q1 D IDELAY RGMII_RXD[3:0] Q2 ODDR D1 D2 Q ODELAY IBUF OBUF RGMII_TXC UG194_6_17_080409 R
R Reduced Gigabit Media Independent Interface (RGMII) At 1 Gb/s, all external logic is clocked at 125 MHz. At 100 Mb/s and 10 Mb/s, the logic is clocked at 25 MHz and 2.5 MHz, respectively. To maintain the correct data rate at the client interface, clock enable signals are output on EMAC#CLIENTTXCLIENTCLKOUT for the transmitter logic, and EMAC#CLIENTRXCLIENTCLKOUT for the receiver logic. These signals are High during 1 Gb/s operation and toggle on each clock edge at slower speeds. These are used to enable the client interface logic. Due to the timing relationship between the RGMII transmit clock and the internal client clock signals, the TX_ACK signal (CLIENTEMAC#TXACK) is registered at the output of the Ethernet MAC when operating at speeds below 1 Gb/s. At 1 Gb/s, the register is bypassed. RGMII_TXC is derived from the Ethernet MAC by routing the EMAC#PHYTXGMIIMIICLKOUT port to an IOB DDR output register, followed by an ODELAY element and an OBUF (which is then connected to the PHY). The ODELAY element is used to generate 2 ns of skew required between RGMII_TXC and RGMII_TXD at the FPGA device pads. This delay is specified in the Hewlett Packard RGMII Specification, v2.0 to provide setup and hold times on the external interface. RGMII_RXC is generated by the PHY and connected to PHYEMAC#RXCLK via an IBUFG and a BUFG. Fixed-mode IDELAYs are instantiated on the RGMII clock and data lines. These are set to sample a 1 ns setup, 1 ns hold window at the device pads. RGMII_RXC drives all receive logic. The CLIENTEMAC#DCMLOCKED port must be tied High. This clocking scheme requires two fewer BUFGs than the default scheme detailed in Figure 6-15. TEMAC User Guide www.xilinx.com 163 UG194 (v1.10) February 14, 2011
Page 1 and 2:
Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4:
Date Version Revision 08/08/07 (con
Page 5 and 6:
Date Version Revision 10/01/09 1.9
Page 7 and 8:
Table of Contents Guide Contents .
Page 9 and 10:
R Chapter 5: MDIO Interface Introdu
Page 11 and 12:
R About This Guide Guide Contents P
Page 13 and 14:
R Additional Support Resources User
Page 15 and 16:
R Typographical Online Document Use
Page 17 and 18:
Introduction Key Features R Chapter
Page 19 and 20:
R Typical Ethernet Application Over
Page 21 and 22:
R Number of Bytes Physical Sublayer
Page 23 and 24:
R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26:
R Using the Embedded Ethernet MAC T
Page 27 and 28:
R Ethernet MAC Overview Chapter 2 T
Page 29 and 30:
Generic Host Bus DCR Bus R Flow Con
Page 31 and 32:
R Ethernet MAC Primitive Ethernet M
Page 33 and 34:
R Ethernet MAC Signal Descriptions
Page 35 and 36:
R Table 2-3: Receive Client Interfa
Page 37 and 38:
R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40:
R Table 2-8: PHY Data and Control S
Page 41 and 42:
R Table 2-12: PCS/PMA Signals Table
Page 43 and 44:
R Table 2-16: Mode Configuration At
Page 45 and 46:
R Table 2-17: MAC Configuration Att
Page 47 and 48:
R Table 2-17: MAC Configuration Att
Page 49 and 50:
R Table 2-18: Physical Interface At
Page 51 and 52:
R Client Interface Chapter 3 This c
Page 53 and 54:
R Normal Frame Transmission CLIENTE
Page 55 and 56:
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58:
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60:
R Normal Frame Transmission PHYEMAC
Page 61 and 62:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64:
R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66:
R Frame Reception with Errors CLIEN
Page 67 and 68:
R Receive (RX) Client: 8-Bit Interf
Page 69 and 70:
R Receive (RX) Client: 16-Bit Inter
Page 71 and 72:
R Address Filtering Address Filteri
Page 73 and 74:
R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76:
R Transmitting a PAUSE Control Fram
Page 77 and 78:
R Operation Figure 3-30 illustrates
Page 79 and 80:
R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82:
R Table 3-3: Bit Definitions for th
Page 83 and 84:
R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86:
R Host/DCR Bus Interfaces This chap
Page 87 and 88:
HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90:
R Table 4-3: Receiver Configuration
Page 91 and 92:
R Table 4-5: Flow Control Configura
Page 93 and 94:
R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96:
R Table 4-9: Unicast Address (Word
Page 97 and 98:
R Table 4-13: Address Filter Mode 0
Page 99 and 100:
R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102:
R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104:
R Using the DCR Bus The directly ad
Page 105 and 106:
R Table 4-18: DCR Control Register
Page 107 and 108:
R Using the DCR Bus The IRENABLE_e#
Page 109 and 110:
R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 155 and 156: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 161: R Reduced Gigabit Media Independent
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214:
R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216:
R Clock Definitions and Frequencies
Page 217 and 218:
R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220:
R Clock Enables Modifications Relat
Page 221 and 222:
R Additional Attributes Table C-2:
Page 223 and 224:
R Appendix D Differences between So
show all

Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?