Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Gigabit Media Independent Interface (GMII)
to PHYEMAC#MIITXCLK through an IBUF. The frequency of GMII_RX_CLK, generated
from the PHY, is 2.5 MHz, 25 MHz, or 125 MHz, depending on the operating speed of the
Ethernet MAC. Fixed-mode IDELAYs are used on the GMII_RX_CLK and GMII_RXD
inputs to align the clock and data. These are set to sample a 2 ns setup, 0 ns hold window
at the device pads.The CLIENTEMAC#DCMLOCKED port must be tied High.
The GMII_TX_CLK is derived from the Ethernet MAC, routed through an OBUF, and then
connected to the PHY. Because GMII_TX_CLK is derived from
EMAC#PHYTXGMIIMIICLKOUT, its frequency automatically changes between 125 MHz,
25 MHz, or 2.5 MHz, depending on the speed setting of the Ethernet MAC.
GMII Clock Management for Tri-Speed Operation Using Byte PHY
Figure 6-9 shows an alternative clock management scheme for the tri-speed GMII
interface. This clock management scheme is used when the EMAC#_BYTEPHY attribute is
set to TRUE. In this scheme, the EMAC datapath is 8 bits wide at both the client and the
physical interfaces at all speeds. At 1 Gb/s, all external logic is clocked at 125 MHz. At
100 Mb/s and 10 Mb/s, the logic is clocked at 12.5 MHz and 1.25 MHz, respectively. DDR
input and output registers are used to achieve the 25 MHz and 2.5 MHz 4-bit data rate at
speeds below 1 Gb/s, resulting in a scheme that utilizes two clock buffers less than
Figure 6-8. Alignment logic must be provided on the receiver side to align the start of
frame delimiter in the 8-bit data input to the EMAC.
TEMAC User Guide www.xilinx.com 149
UG194 (v1.10) February 14, 2011