Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 4: Host/DCR Bus Interfaces The register definitions for the DCR bridge registers are shown in Table 4-16 to Table 4-19. The DCR registers (dataRegMSW, dataRegLSW, cntlReg, and RDYstatus_e#) and the DCR bridge registers (IRSTATUS_e#, IRENABLE_e#, and MIIMWRDATA) use the big-endian bit numbering convention. The Ethernet MAC host registers, such as Receiver Configuration (Word 0) (host address 0x200) register, use the little-endian bit numbering convention. In the DCR bridge implementation, there is no conversion to or from big endian to little endian. The bit positions are mapped directly in a one-to-one correspondence (big-endian bit [0] is mapped directly to little-endian bit [31], bit [1] is mapped directly to little endian bit [30], and so forth). Table 4-16: DCR Data Register dataRegMSW MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dataRegMSW Bit Description Default Value [0:31] Data. Data input from the DCR bus for the Ethernet MAC registers or other accessible registers is written into this register. The most significant word of data is read out from the Ethernet MAC registers or other registers and deposited into this register. Because dataRegMSW is shared between EMAC0 and EMAC1, data is overwritten by a read/write operation to the other Ethernet MAC. The MSW data register is used when reading from the General Address table and for a read from FPGA logic registers. For all other transactions, only the LSW data register is used. Table 4-17: DCR Data Register dataRegLSW MSB Undefined 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dataRegLSW Bit Description Default Value DCR Data Register (dataRegLSW) [0:31] Data. Data input from the DCR bus for the Ethernet MAC registers or other registers is written into this register. The least significant word of data is read out from the Ethernet MAC registers or other registers is deposited into this register. Because dataRegLSW is shared between EMAC0 and EMAC1, data is overwritten by a read/write operation to the other Ethernet MAC. Undefined 104 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 LSB LSB R
R Table 4-18: DCR Control Register cntlReg MSB . Using the DCR Bus 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED TEMAC User Guide www.xilinx.com 105 UG194 (v1.10) February 14, 2011 WEN RESERVED ADDRESS_CODE Bit Description Default Value [0:15] Reserved. All 0s [16] Write Enable. When this bit is asserted, the data in either dataRegLSW or dataRegMSW is written to the Ethernet MAC host interface. When this bit is deasserted, the operation to be performed is read. [17:21] Reserved. All 0s [22:31] Address Code. The DCR bus bridge translates the address code for this transaction into the appropriate signals on the Ethernet MAC host interface. See Table 4-15, page 103 for a description of address codes. Table 4-19: DCR Ready Status Register RDYstatus_e# (Read Only) MSB 0 All 0s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED DCR RDY RESERVED Bit Description Default Value [0:14] Reserved. All 0s [15] DCR Bridge Ready bit. High when all of the bits in RDYstatus_e0 or RDYstatus_e1 are High. 1 [16:24] Reserved. All 0s [25] Configuration Write-Ready bit. 1 [26] Configuration Read-Ready bit. 1 [27] Address Filter Write-Ready bit. 1 [28] Address Filter Read-Ready bit. 1 [29] MDIO Write-Ready bit. 1 [30] MDIO Read-Ready bit. 1 [31] FPGA Logic Read-Ready bit. 1 CFG WR CFG RR AF WR AF RR MIIM WR MIIM RR LSB LSB FABR RR
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103: R Using the DCR Bus The directly ad
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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