Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
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GTX_CLK<br />
TX Client<br />
Logic<br />
RX Client<br />
Logic<br />
R<br />
IBUF<br />
BUFG<br />
BUFG<br />
E<strong>MAC</strong>#<br />
PHYE<strong>MAC</strong>#GTXCLK<br />
PHYE<strong>MAC</strong>#TXGMIIMIICLKIN<br />
E<strong>MAC</strong>#PHYTXGMIIMIICLKOUT<br />
CLIENTE<strong>MAC</strong>#TXCLIENTCLKIN<br />
E<strong>MAC</strong>#CLIENTTXCLIENTCLKOUT<br />
CLIENTE<strong>MAC</strong>#RXCLIENTCLKIN<br />
CLIENTE<strong>MAC</strong>#DCMLOCKED<br />
E<strong>MAC</strong>#PHYTXD[3:0]<br />
E<strong>MAC</strong>#PHYTXD[7:4]<br />
PHYE<strong>MAC</strong>#MIITXCLK<br />
E<strong>MAC</strong>#CLIENTRXCLIENTCLKOUT<br />
PHYE<strong>MAC</strong>#RXCLK<br />
PHYE<strong>MAC</strong>#RXD[3:0]<br />
PHYE<strong>MAC</strong>#RXD[7:4]<br />
Notes:<br />
1) A regional buffer (BUFR) can replace this BUFG.<br />
In addition, the clock input of IDDR can be driven by a BUFIO.<br />
Refer to UG190, <strong>Virtex</strong>-5 <strong>FPGA</strong> User Guide for BUFR usage guidelines.<br />
Reduced Gigabit Media Independent Interface (RGMII)<br />
BUFG (1)<br />
Figure 6-15: <strong>Tri</strong>-<strong>Mode</strong> RGMII v2.0 Clock Management<br />
RGMII_TXC is derived from the <strong>Ethernet</strong> <strong>MAC</strong> by routing the<br />
E<strong>MAC</strong>#PHYTXGMIIMIICLKOUT port to an IOB DDR output register, followed by an<br />
ODELAY element and an OBUF (which is then connected to the PHY). The ODELAY<br />
element is used to generate 2 ns of skew required between RGMII_TXC and RGMII_TXD at<br />
the <strong>FPGA</strong> device pads. This delay is specified in the Hewlett Packard RGMII Specification,<br />
v2.0 to provide setup and hold times on the external interface.<br />
The E<strong>MAC</strong>#CLIENTTXCLIENTCLKOUT output port connects to the<br />
CLIENTE<strong>MAC</strong>#TXCLIENTCLKIN input port and transmitter client logic in the <strong>FPGA</strong> logic<br />
through a BUFG. The receiver client clocking is similar.<br />
RGMII_RXC is generated by the PHY and connected to PHYE<strong>MAC</strong>#RXCLK via an IBUFG<br />
and a BUFG. Fixed-mode IDELAYs are instantiated on the RGMII clock and data lines.<br />
These are set to sample a 1 ns setup, 1 ns hold window at the device pads. The<br />
CLIENTE<strong>MAC</strong>#DCMLOCKED port must be tied High.<br />
TE<strong>MAC</strong> User Guide www.xilinx.com 159<br />
<strong>UG194</strong> (v1.10) February 14, 2011<br />
1<br />
0<br />
ODDR<br />
D1<br />
D2<br />
Q<br />
OBUF<br />
RGMII_TXD[3:0]<br />
(1)<br />
BUFG IBUFG<br />
IDELAY<br />
RGMII_RXC<br />
IDDR<br />
Q1 D IDELAY<br />
RGMII_RXD[3:0]<br />
Q2<br />
ODDR<br />
D1<br />
D2<br />
Q<br />
ODELAY<br />
IBUF<br />
OBUF<br />
RGMII_TXC<br />
<strong>UG194</strong>_6_15_080409