Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview The Ethernet MACs within the block are the same. When describing the functionality of the Ethernet MACs in this document, EMAC# is used when the description is for EMAC0 or EMAC1. Each Ethernet MAC has an independent transmit (TX) and receive (RX) datapath, providing full-duplex capability. The host interface of the Ethernet MAC provides access to the configuration registers of both Ethernet MACs, illustrated in Figure 2-1. The host interface can be accessed using either the generic host bus or the DCR bus through the DCR bridge. The physical interface of each Ethernet MAC can be configured as either MII, GMII, RGMII, SGMII, or 1000BASE-X. Figure 2-1 shows all possible data ports for the physical interface; however, only one set of these TX and RX interfaces is active per Ethernet MAC, based on the selected physical interface configuration. The individual Ethernet MACs can be configured to have different physical interfaces. Each Ethernet MAC has an optional Management Data I/O interface (MDIO), allowing access to the management registers of an external PHY or access to the physical interface management registers within the Ethernet MAC (used only when it is configured in either 1000BASE-X or SGMII modes). Each Ethernet MAC outputs statistics vectors containing information about the Ethernet frames seen on its transmit and receive datapaths. The statistics vectors are multiplexed to reduce the number of pins at the block boundary. An external module (Statistics IP0 and/or Statistics IP1) can be designed and implemented in the FPGA logic to accumulate all the TX and RX datapath statistics of each Ethernet MAC. Additional information on interfacing to the statistics block is provided in Chapter 7, “Interfacing to a Statistics Block.” A detailed functional block diagram of a single Ethernet MAC is shown in Figure 2-2. This is labeled as EMAC#, which can represent either EMAC0 or EMAC1 from Figure 2-1. 28 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
Generic Host Bus DCR Bus R Flow Control Interface Host Interface DCR Bridge EMAC# TX RX 16- or 8-bit Client Interface Transmit Engine Flow Control Receive Engine Address Filter Registers MDIO Interface MAC Configuration Registers TX RX Statistics Clock Management Architecture Description Figure 2-2: Functional Block Diagram of Single Ethernet MAC (with Host Interface) MII/GMII/RGMII Interface to External PHY GTP/GTX Transceiver Interface MDIO Interface to External PHY The client interface shows the user transmit and receive interfaces connected to the transmit and receive engines of the Ethernet MAC, respectively. For detailed information on the protocol for data transmission and reception on this interface, refer to “Client Interface,” page 51. The flow control interface allows the client logic to force the physical layer to stop sending frames until the client is capable of accepting more. A description of how to use this interface from the client logic can be found in “Flow Control Block,” page 73. The Ethernet MAC has a programmable address filter to accept or reject incoming frames on the receive datapath. The full functionality of the Ethernet MAC address filter is described in “Address Filtering,” page 71. The shared host interface can access the MAC Configuration registers and the Address Filter registers. See “Host/DCR Bus Interfaces,” page 85 to learn how to interface to any host via the generic host bus, or how to interface to a processor through the DCR bus. The host interface can also initiate transactions on the MDIO interface, when the MDIO interface is enabled. This allows the host interface to access the PCS Management Registers within the Ethernet MAC, when it is configured in 1000BASE-X or SGMII mode. It is also possible for the host interface to initiate transactions via the MDIO interface to an external PHY device. When the MDIO interface is enabled and the host interface is disabled, an external device can still access the PCS Management Registers of the Ethernet MAC when it is configured in 1000BASE-X or SGMII mode. Information on these configurations and on using the MDIO protocol to access PCS Management registers can be found in “MDIO Interface,” page 115. TEMAC User Guide www.xilinx.com 29 UG194 (v1.10) February 14, 2011 MII/GMII/RGMII Interface TX RX TX RX PCS/PMA Sublayer PCS Management Registers MDIO Arbitration UG194_c2_02_062309
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27: R Ethernet MAC Overview Chapter 2 T
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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