Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview RX Client TX Client Flow Control Generic Host Bus DCR Bus EMAC#CLIENTRXCLIENTCLKOUT CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXD[15:0] EMAC#CLIENTRXDVLD EMAC#CLIENTRXDVLDMSW EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXBADFRAME EMAC#CLIENTRXFRAMEDROP EMAC#CLIENTRXSTATS[6:0] EMAC#CLIENTRXSTATSBYTEVLD EMAC#CLIENTRXSTATSVLD EMAC#CLIENTTXCLIENTCLKOUT CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXD[15:0] CLIENTEMAC#TXDVLD CLIENTEMAC#TXDVLDMSW EMAC#CLIENTTXACK CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT CLIENTEMAC#TXIFGDELAY[7:0] CLIENTEMAC#TXFIRSTBYTE EMAC#CLIENTTXSTATS EMAC#CLIENTTXSTATSBYTEVLD EMAC#CLIENTTXSTATSVLD CLIENTEMAC#PAUSEREQ CLIENTEMAC#PAUSEVAL[15:0] HOSTADDR[9:0] HOSTCLK HOSTMIIMSEL HOSTOPCODE[1:0] HOSTREQ HOSTMIIMRDY HOSTRDDATA[31:0] HOSTWRDATA[31:0] HOSTEMAC1SEL DCREMACENABLE EMACDCRACK EMACDCRDBUS[0:31] DCREMACABUS[0:9] DCREMACCLK DCREMACDBUS[0:31] DCREMACREAD DCREMACWRITE DCRHOSTDONEIR EMAC# Primitive Figure 2-3: Ethernet MAC Primitive RESET CLIENTEMAC#DCMLOCKED PHYEMAC#GTXCLK EMAC#SPEEDIS10100 EMAC#PHYTXGMIIMIICLKOUT PHYEMAC#TXGMIIMIICLKIN PHYEMAC#RXCLK PHYEMAC#RXD[7:0] PHYEMAC#RXDV PHYEMAC#RXER PHYEMAC#MIITXCLK EMAC#PHYTXCLK EMAC#PHYTXD[7:0] EMAC#PHYTXEN EMAC#PHYTXER PHYEMAC#COL PHYEMAC#CRS PHYEMAC#SIGNALDET PHYEMAC#PHYAD[4:0] EMAC#PHYENCOMMAALIGN EMAC#PHYLOOPBACKMSB EMAC#PHYMGTRXRESET EMAC#PHYMGTTXRESET EMAC#PHYPOWERDOWN EMAC#PHYSYNCACQSTATUS PHYEMAC#RXCLKCORCNT[2:0] PHYEMAC#RXBUFSTATUS[1:0] PHYEMAC#RXCHARISCOMMA PHYEMAC#RXCHARISK PHYEMAC#RXCHECKINGCRC PHYEMAC#RXCOMMADET PHYEMAC#RXDISPERR PHYEMAC#RXLOSSOFSYNC[1:0] PHYEMAC#RXNOTINTABLE PHYEMAC#RXRUNDISP PHYEMAC#RXBUFERR EMAC#CLIENTANINTERRUPT EMAC#PHYTXCHARDISPMODE EMAC#PHYTXCHARDISPVAL EMAC#PHYTXCHARISK PHYEMAC#TXBUFERR EMAC#PHYMCLKOUT PHYEMAC#MCLKIN PHYEMAC#MDIN EMAC#PHYMDOUT EMAC#PHYMDTRI 32 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 Physical Interface GTP/GTX Transceiver Management Data I/O UG194_2_03_072306 R
R Ethernet MAC Signal Descriptions Ethernet MAC Signal Descriptions This section defines all of the Ethernet MAC primitive signals. The signals are divided into the following categories: “Client-Side Signals” “Host Interface Signals” “Management Data Input/Output (MDIO) Signals” “MII/GMII/RGMII Physical Interface Signals” “RocketIO Serial Transceiver Signals” “Global Clock and Reset Signals” All the signals available in the Ethernet MAC primitive are described in this section. The # symbol denotes the EMAC0 or EMAC1 signals. Client-Side Signals TX Client Signals Table 2-2: Transmit Client Interface Signals Table 2-2 describes the client-side transmit signals in the Ethernet MAC. These signals are used to transmit data from the client to the Ethernet MAC. Signal Direction Description CLIENTEMAC#TXD[15:0] Input Frame data for transmit. The datapath can be configured to be either 8 or 16 bits wide. Bits [7:0] are used for 8-bit width. The 16-bit interface is available only in 1000BASE-X PCS/PMA mode. See “Transmit (TX) Client: 16-Bit Interface,” page 60. CLIENTEMAC#TXDVLD Input Asserted by the client to indicate a valid data input at CLIENTEMAC#TXD[7:0]. CLIENTEMAC#TXDVLDMSW Input When the width of CLIENTEMAC#TXD is set to 16 bits, this signal denotes an odd number of bytes in the transmit datapath. In the frame with an odd number of bytes, the CLIENTEMAC#TXD[7:0] is valid on the last byte. When the width of CLIENTEMAC#TXD is set to 8 bits, this signal is connected to ground. CLIENTEMAC#TXFIRSTBYTE Input This signal should be tied Low. CLIENTEMAC#TXIFGDELAY[7:0] Input Configurable interframe gap (IFG) adjustment for full-duplex mode. CLIENTEMAC#TXUNDERRUN Input Asserted by the client to force the Ethernet MAC to corrupt the current frame. CLIENTEMAC#TXCLIENTCLKIN Input See “Ethernet MAC Clocks,” page 205. EMAC#CLIENTTXACK Output Handshake signal – Asserted when the Ethernet MAC accepts the first byte of data. On the next and subsequent rising clock edges, the client must provide the remainder of the frame data. See “Normal Frame Transmission Across Client Interface,” page 53. TEMAC User Guide www.xilinx.com 33 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31: R Ethernet MAC Primitive Ethernet M
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114:
R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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Page 151 and 152:
Page 153 and 154:
R Reduced Gigabit Media Independent
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Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168:
R Ethernet MAC to RocketIO Serial T
Page 169 and 170:
TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
Page 183 and 184:
R Serial Gigabit Media Independent
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Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
Page 203 and 204:
R Pinout Guidelines Appendix A Xili
Page 205 and 206:
R Ethernet MAC Clocks Appendix B Th
Page 207 and 208:
TX Client Logic RX Client Logic R
Page 209 and 210:
R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
Page 213 and 214:
R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216:
R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
Page 221 and 222:
R Additional Attributes Table C-2:
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R Appendix D Differences between So
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