Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 5: MDIO Interface Introduction to MDIO MDIO Bus System The MDIO interface for 1 Gb/s operation (and slower speeds) is defined in IEEE Std 802.3, clause 22. This two-wire interface consists of a clock (MDC) and a shared serial data line (MDIO). The maximum permitted frequency of MDC is set at 2.5 MHz. Figure 5-1 illustrates an example MDIO bus system. An Ethernet MAC is shown as the MDIO bus master (the Station Management (STA) entity). Two PHY devices are shown connected to the same bus, both are MDIO slaves (MDIO Managed Device (MMD) entities). MAC (STA) Host Bus Interface MDIO Master MDIO MDC PHY1 (MMD) Configuration Registers 0 to 31 (REGAD) MDIO Slave PHY2 (MMD) Configuration Registers 0 to 31 (REGAD) MDIO Slave Figure 5-1: Typical MDIO-Managed System Physical Address (PHYAD) = 1 Physical Address (PHYAD) = 2 UG194_5_01_072306 Described simply, the MDIO bus system is a standardized interface for accessing the configuration and status registers of Ethernet PHY devices. In the example illustrated, the Management Host Bus Interface of the Ethernet MAC is able to access the configuration and status registers of two PHY devices via the MDIO bus. 116 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
MDC MDIO R MDIO Transactions Introduction to MDIO All transactions, read or write, are initiated by the MDIO master. All MDIO slave devices, when addressed, must respond. MDIO transactions take the form of an MDIO frame, containing fields for transaction type, address and data. This MDIO frame is transferred across the MDIO wire synchronously to MDC. The following abbreviations are used in this chapter: Table 5-1: Abbreviations Used in this Chapter Abbreviation Definition Write Transaction Figure 5-2 shows a write transaction frame across the MDIO, as defined by OP = 0b01. The addressed PHY device (with physical address PHYAD) takes the 16-bit word in the Data field and writes it to the register at REGAD. Read Transaction OP Operation code (read or write) PHYAD Physical address PRE Preamble REGAD Register address ST Start of frame TA Turnaround STA Drives MDIO Z Z 1 1 1 0 1 0 1 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 1 0 D15 D13 D11 D9 D7 D5 D3 D1 Z Z D14 D12 D10 D8 D6 D4 D2 D0 IDLE 32 bits PRE ST OP PHYAD REGAD TA 16-Bit WRITE DATA IDLE Figure 5-2: MDIO Write Transaction UG194_5_02_032406 Figure 5-3 shows a read transaction as defined by OP = 0b10. The addressed PHY device (with physical address PHYAD) takes control of the MDIO wire during the turnaround cycle and then returns the 16-bit word from the register at REGAD. TEMAC User Guide www.xilinx.com 117 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115: R MDIO Interface Chapter 5 This cha
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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