Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...
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Table 2-18: Physical Interface Attributes (Cont’d)<br />
Attribute Type Description<br />
<strong>Ethernet</strong> <strong>MAC</strong> Attributes<br />
Attribute to Configure Auto-negotiation Parameters See the following sections for details on attribute value<br />
settings for Physical interface settings of SGMII or 1000BASE-<br />
X:<br />
SGMII: “Auto-Negotiation Link Timer,” page 197.<br />
1000BASE-X: “Auto-Negotiation Link Timer,” page 175.<br />
E<strong>MAC</strong>#_LINKTIMERVAL[8:0] 9-bit<br />
Binary<br />
Table 2-19: Address Filter Attributes<br />
Programmable auto-negotiation link timer value.<br />
Attribute Type Description<br />
Attribute to Configure Default Register Value for<br />
the Unicast Address Register<br />
E<strong>MAC</strong>#_UNICASTADDR[47:0] 48-bit<br />
Binary<br />
Table 2-20: DCR Base Address Attributes<br />
This attribute sets the default value of the Unicast Address[47:0] in<br />
the Unicast Address (Word 0) and (Word 1) registers. See “Unicast<br />
Address (Word 0),” page 95 and “Unicast Address (Word 1),” page<br />
95 for register details.<br />
This 48-bit attribute is used to set the <strong>Ethernet</strong> <strong>MAC</strong> unicast<br />
address used by the address filter block to see if the incoming frame<br />
is destined for the <strong>Ethernet</strong> <strong>MAC</strong>.<br />
The address is ordered for the least significant byte in the register<br />
to have the first byte transmitted or received; for example, an<br />
<strong>Ethernet</strong> <strong>MAC</strong> address of 06-05-04-03-02-01 is stored in bits [47:0] as<br />
0x010203040506.<br />
This default value for the unicast address can be overridden by<br />
software through the host interface.<br />
Attribute Type Description<br />
Attribute to Configure Default Value for DCR<br />
Base Address<br />
E<strong>MAC</strong>#_DCRBASEADDR[7:0] 8-bit<br />
Binary<br />
See “Using the DCR Bus,” page 101 for a description of how the<br />
DCR Base Addresses are used to access different registers.<br />
This attribute allows separate DCR base addresses to be used for<br />
each <strong>Ethernet</strong> <strong>MAC</strong>.<br />
TE<strong>MAC</strong> User Guide www.xilinx.com 49<br />
<strong>UG194</strong> (v1.10) February 14, 2011