Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 5: MDIO Interface Table 5-3: Control Register (Register 0) (Cont’d) Bit(s) Name Description Type Default Value 0.10 Isolate 1 = Electrically isolate the PHY from GMII. 0 = Normal operation. 0.9 Restart Auto- Negotiation 1 = Restart Auto-Negotiation process. 0 = Normal operation. 0.8 Duplex Mode The Ethernet MAC always returns a 1 for this bit to signal full-duplex mode. 0.7 Collision Test The Ethernet MAC always returns a 0 for this bit to disable COL test. 0.6 Speed Selection (MSB) 0.5 Unidirection al Enable The Ethernet MAC always returns a 1 for this bit. Together with bit 0.13, speed selection of 1000 Mb/s is identified. Enable transmit regardless of whether a valid link has been established. 0.4:0 Reserved Always returns zeros, writes ignored. Table 5-4: Status Register (Register 1) Read/Write EMAC#_PHYISOLATE “Physical Interface Attributes” Read/Write Self Clearing 124 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 0 Returns 1 1 Returns 0 0 Returns 1 1 Read/Write EMAC#_UNIDIRECTION_ENABLE “Physical Interface Attributes” Returns 0s 00000 Bit(s) Name Description Type Default Value 1.15 100BASE-T4 The Ethernet MAC always returns a 0 for this bit because 100BASE-T4 is not supported. 1.14 100BASE-X Full Duplex 1.13 100BASE-X Half Duplex 1.12 10 Mb/s Full Duplex 1.11 10 Mb/s Half Duplex 1.10 100BASE-T2 Full Duplex 1.9 100BASE-T2 Half Duplex The Ethernet MAC always returns a 0 for this bit because 100BASE-X full duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 100BASE-X half duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 10 Mb/s full duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 10 Mb/s half duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 100BASE-T2 full duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 100BASE-T2 half duplex is not supported. 1.8 Extended Status The Ethernet MAC always returns a 1 for this bit, indicating the presence of the extended register (Register 15). Returns 0 0 Returns 0 0 Returns 0 0 Returns 0 0 Returns 0 0 Returns 0 0 Returns 0 0 Returns 1 1 R
R Table 5-4: Status Register (Register 1) (Cont’d) 1.7 Unidirectional Ability Link Status 1000BASE-X PCS/PMA Management Registers Bit(s) Name Description Type Default Value 1.6 MF Preamble Suppression 1.5 Auto- Negotiation Complete Always returns a 1, writes ignored. Returns 1 1 The Ethernet MAC always returns a 1 for this bit to indicate the support of management frame preamble suppression. 1 = Auto-Negotiation process completed. 0 = Auto-Negotiation process not completed. 1.4 Remote Fault 1 = Remote fault condition detected. 0 = No remote fault condition detected. 1.3 Auto- Negotiation Ability The Ethernet MAC always returns a 1 for this bit, indicating that the PHY is capable of autonegotiation. 1.2 Link Status 1 = Link is up 0 = Link is down (or has been down) Latches 0 if Link Status goes down. Clears to current Link Status on read. See the following Link Status section for further details. 1.1 Jabber Detect The Ethernet MAC always returns a 0 for this bit because jabber detect is not supported. 1.0 Extended Capability The Ethernet MAC always returns a 0 for this bit because no extended register set is supported. Returns 1 1 Read Only 0 Read Only Self Clearing on read Returns 1 1 Read Only Self clearing on read Returns 0 0 Returns 0 0 When Link Status is High, the link is valid and has remained valid since this register was last read. Synchronization of the link has been obtained and Auto Negotiation (if enabled) has completed. When Low, either: A valid link has not been established. Link synchronization has failed or Auto Negotiation (if enabled) has failed to complete. Link synchronization was lost at some point because this register was previously read. However, the current link status can be valid. Read this register a second time to get confirmation of the current link status. Regardless of whether Auto Negotiation is enabled or disabled, there can be some delay to the deassertion of Link Status following the loss of synchronization of a previously successful link. This is due to the Auto Negotiation state machine, which requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the IEEE Std 802.3 specification (the an_sync_status variable). TEMAC User Guide www.xilinx.com 125 UG194 (v1.10) February 14, 2011 0 0
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123: R 1000BASE-X PCS/PMA Management Reg
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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