Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 5: MDIO Interface
SGMII Management Registers
FPGA
PCS/PMA Sublayer
MAC TX
Interface
MAC RX
Interface
MDIO
Interface
Figure 5-8 shows the PCS/PMA sublayer block in an SGMII implementation. The
PCS/PMA sublayer of the Ethernet MAC, when performing the SGMII standard, contains
PCS Management registers as listed in Table 5-14. These registers are described in further
detail in Table 5-15 through Table 5-25.
PCS Transmit
Engine
Auto-Negotiation
PCS Receive Engine
and
Synchronization
PCS Management
Registers
Figure 5-8: SGMII Logic and Physical Connections
10BASE-T
100BASE-T
1000BASE-T
UG194_5_08_072809
These registers contain information relating to the operation of the system, including the
status of both the SGMII link and the physical Ethernet link (PHY link). Refer to Figure 5-8.
Additionally, these registers are directly involved in the operation of the SGMII Auto-
Negotiation function which occurs between the Ethernet MAC and the external PHY
device, illustrated as a Tri-speed BASE-T PHY in Figure 5-8. (see “SGMII Auto-
Negotiation,” page 196).
130 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
GTP/GTX Transceiver
TX+
TX-
RX+
RX-
SGMII
Link
PHY
Table 5-14: SGMII Configuration Registers for 1000BASE-X PCS/PMA
Register
Address
(REGAD)
0 “SGMII Control Register (Register 0)”
1 “SGMII Status Register (Register 1)”
Register Name
PHY
Link
TX
Twisted
Copper
Pair
RX
R