Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

DCR Offset
0x1
MSB
R
Using the DCR Bus
4. Write to the dataRegLSW register the general address [47:32] with the write mask bit
and the value of the general address table register to be accessed.
5. Write to cntlReg register with the address for general address word 1 (0x38C). Set the
write enable bit.
6. Poll the RDYstatus_e# register until the address configuration write bit is set or wait
until the DCRHOSTDONEIR interrupt is asserted.
To write the general address 0xFACEDEAFCAFE to the general address table register 0x1 of
EMAC1:
// Write the general address[31:0] to the dataRegLSW register
dcr_write(EMAC1_DCRBASEADDR + 1, 0xDEAFCAFE);
// Write the address of EMAC1 General Address Word 0 register to the
// cntlReg_e1 register
dcr_write(EMAC1_DCRBASEADDR + 2, 0x00008388);
// Poll the RDYstatus_e1 register
while ( !(dcr_read(EMAC1_DCRBASEADDR + 3) & 0x00010000) );
// MULTI_ADDR Register 1 of AF Block
// Write the general address [47:32] with the MULTI_ADDR RNW
// write mask bit deasserted to the dataRegLSW register
dcr_write(EMAC1_DCRBASEADDR + 1, 0x0001FACE);
// Write the address of EMAC1 General Address Word 1 register to the
// cntlReg_e1 register
dcr_write(EMAC1_DCRBASEADDR + 2, 0x0000838C);
// Poll the RDYstatus_e1 register
while ( !(dcr_read(EMAC1_DCRBASEADDR + 3) & 0x00010000) );
PCS/PMA Sublayer or External Device Access via MDIO
MDIO register reads take a multiple number of host clock cycles depending on the
physical interface device. To write to any of the PCS layer registers (“1000BASE-X
PCS/PMA Management Registers,” page 122), the data must be written to the
MIIMWRDATA register. The physical address (PHYAD) and PCS register number
(REGAD) are written to the DCR dataRegLSW register for both read and write operations.
Writing the address code 0x3B4 to the control register indicates a request for an MDIO
transaction. The format for writing the PHYAD and REGAD into the dataRegLSW register
is shown in Figure 4-9. To access the internal PCS/PMA sublayer registers, the PHYAD
should match that set on the PHYEMAC#PHYAD[4:0] input port. The MDIO interface is
described in detail in Chapter 5.
0 22 26 27 31
PHYAD
LSB
REGAD
15 PCS Sublayer Managed Register Block 0
Control Register
PHY Identifier Register
Auto-Negotiation Advertisement Register
Figure 4-9: MDIO Address Register to Access PCS Sublayer Register Block
UG194_4_09_072306
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UG194 (v1.10) February 14, 2011
REGAD
0
1
2
3
4
MSB
Status Register
PHY Identifier Register
LSB