Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview Table 2-2: Transmit Client Interface Signals (Cont’d) Signal Direction Description EMAC#CLIENTTXCOLLISION Output Asserted by the Ethernet MAC to signal a collision on the medium. Any transmission in progress must be aborted. This signal is always deasserted in full-duplex mode. EMAC#CLIENTTXRETRANSMIT Output Asserted by the Ethernet MAC at the same time as the EMAC#CLIENTTXCOLLISION signal. The client should resupply the aborted frame to the Ethernet MAC for retransmission. This signal is always deasserted in full-duplex mode. EMAC#CLIENTTXSTATS Output The statistics data on the last data frame sent. The 32-bit TX raw statistics vector is output by one bit per cycle for statistics gathering. See “Transmitter Statistics Vector,” page 78. EMAC#CLIENTTXSTATSBYTEVLD Output Asserted if an Ethernet MAC frame byte is transmitted (including destination address to FCS). This is valid on every TX clock cycle. EMAC#CLIENTTXSTATSVLD Output Asserted by the Ethernet MAC after a frame transmission to indicate a valid EMAC#CLIENTTXSTATS output. See “Transmitter Statistics Vector,” page 78. EMAC#CLIENTTXCLIENTCLKOUT Output See “Ethernet MAC Clocks,” page 205. RX Client Signals Table 2-3: Receive Client Interface Signals Table 2-3 describes the client-side receive signals. These signals are used by the Ethernet MAC to transfer data to the client. Signal Direction Description CLIENTEMAC#RXCLIENTCLKIN Input See “Ethernet MAC Clocks,” page 205. EMAC#CLIENTRXD[15:0] Output Frame data received from the Ethernet MAC. The datapath can be configured to either 8 bits or 16 bits wide. Bits [7:0] are used for 8-bit widths. The 16-bit interface is used in 1000BASE-X PCS/PMA mode. See “Receive (RX) Client: 16-Bit Interface,” page 69. EMAC#CLIENTRXDVLD Output The Ethernet MAC indicates to the client the receipt of valid frame data. EMAC#CLIENTRXFRAMEDROP Output This signal is asserted to notify the client that an incoming receive frames destination address does not match any addresses in the address filter. The signal functions even when the address filter is not enabled. EMAC#CLIENTRXDVLDMSW Output This signal denotes an odd number of bytes in the receive datapath when the width of EMAC#CLIENTRXD is set to 16 bits. In a frame with an odd number of bytes, the EMAC#CLIENTRXD[7:0] byte is valid on the last byte. When the width of EMAC#CLIENTRXD is set to 8 bits, this signal should be left unconnected. EMAC#CLIENTRXGOODFRAME Output This signal is asserted after the last receipt of data to indicate the reception of a compliant frame. 34 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Table 2-3: Receive Client Interface Signals (Cont’d) Signal Direction Description Flow Control Signals Ethernet MAC Signal Descriptions EMAC#CLIENTRXBADFRAME Output This signal is asserted after the last receipt of data to indicate the reception of a non-compliant frame. EMAC#CLIENTRXSTATS[6:0] Output The statistics data on the last received data frame. The 27-bit raw RX statistics vector is multiplexed into a 7-bits-per-RX clock cycle output for statistics gathering. See “Receiver Statistics Vector,” page 81. EMAC#CLIENTRXSTATSBYTEVLD Output Asserted if an Ethernet MAC frame byte (including destination address to FCS) is received. Valid on every RX clock cycle. EMAC#CLIENTRXSTATSVLD Output Asserted by the Ethernet MAC after the end of receiving a frame to indicate a valid EMAC#CLIENTRXSTATS[6:0] output. EMAC#CLIENTRXCLIENTCLKOUT Output See “Ethernet MAC Clocks,” page 205. Table 2-4: Flow Control Interface Signals Table 2-4 describes the signals used by the client to request a flow control action from the transmit engine. The flow control block is designed per the specifications in clause 31 of the IEEE Std 802.3-2002 specification. Flow control frames received by the Ethernet MAC are automatically handled. Signal Direction Description CLIENTEMAC#PAUSEREQ Input Asserted by client to transmit a pause frame. CLIENTEMAC#PAUSEVAL[15:0] Input The amount of pause time for the transmitter as defined in the IEEE Std 802.3-2002 specification. TEMAC User Guide www.xilinx.com 35 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33: R Ethernet MAC Signal Descriptions
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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