Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 2: Ethernet MAC Overview
Host Interface Signals
Generic Host Bus Signals
Table 2-5: Generic Host Bus Signals
Table 2-5 outlines the host bus interface signals.
Signal Direction Description
HOSTCLK Input Clock supplied for running the host.
HOSTOPCODE[1:0] Input Defines the operation to be performed over the MDIO interface. Bit 1 is also used
in configuration register access. See “Using the Host Bus,” page 97.
HOSTADDR[9:0] Input Address of register to be accessed.
HOSTWRDATA[31:0] Input Data bus to write to register.
HOSTRDDATA[31:0] Output Data bus to read from register.
HOSTMIIMSEL Input When asserted, the MDIO interface is accessed. When deasserted, the Ethernet
MAC internal configuration registers are accessed.
HOSTREQ Input Used to signal a transaction on the MDIO interface.
HOSTEMAC1SEL Input This signal is asserted when EMAC1 is being accessed through the host interface
and deasserted when EMAC0 is being accessed through the host interface. It is
ignored when the host interface is not used.
HOSTMIIMRDY Output When High, the MDIO interface has completed any pending transaction and is
ready for a new transaction.
Notes:
1. All signals are synchronous to HOSTCLK and are active High.
2. When using a host processor with the DCR bus, the host bus signals are used to read the optional FPGA logic-based statistics
registers. See Chapter 7, “Interfacing to a Statistics Block.”
36 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
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