Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Date Version Revision
04/28/09 1.8 All chapters:
Changed references to FXT devices to include both TXT and FXT devices.
Replaced the term platform with the term device.
Replaced the term SmartModel with the term SecureIP model.
Chapter 2:
Changed references to GTP transceiver to GTP/GTX transceiver in Figure 2-1,
page 27, Figure 2-2, page 29, and Figure 2-3, page 32.
Chapter 3:
Revised the text of “Client-Supplied FCS Passing” on page 53.
Chapter 5:
Changed references to GTP transceiver to GTP/GTX transceiver in Figure 5-4,
page 119, Figure 5-6, page 121, Figure 5-7, page 122, and Figure 5-8, page 130.
Chapter 6:
Revised Note 1 to indicate the clock input of IFD can be driven by a BUFIO in
Figure 6-3, page 141, Figure 6-8, page 148, Figure 6-14, page 157, and
Figure 6-15, page 159.
Added Note 1 indicating a BUFG buffer can be replaced by a BUFR and the
clock input of IFD can be driven by a BUFIO in Figure 6-4, page 142, Figure 6-6,
page 145, Figure 6-7, page 147, and Figure 6-10, page 152.
Added Note 1 indicating a BUFG buffer can be replaced by a BUFR and the
clock input of IDDR can be driven by a BUFIO in Figure 6-12, page 154,
Figure 6-13, page 156, Figure 6-16, page 160, and Figure 6-17, page 162.
Where a RocketIO® transceiver is shown, added the term RocketIO in
Figure 6-21, page 169, Figure 6-22, page 170, Figure 6-36, page 191, and
Figure 6-37, page 192.
Revised schematic by adding a BUFGMUX to the PHYEMAC#MIITXCLK
input in Figure 6-8, page 148.
Revised schematic by changing the I0 input source for the BUFGMUX on the
PHYEMAC#TXGMIIMIICLKIN input in Figure 6-8, page 148.
Revised schematic by adding a BUFG buffer between the transceiver
REFCLKOUT output and the DCM CLKIN input in Figure 6-22, page 170,
Figure 6-23, page 172, Figure 6-24, page 173, Figure 6-38, page 194, and
Figure 6-39, page 195.
Changed references to GTP transceiver to GTP/GTX transceiver in Figure 6-28,
page 179, Figure 6-29, page 182, Figure 6-33, page 186, and Figure 6-41,
page 198.
Added link to UG198 in “RX Elastic Buffer Implementations” on page 181 and
“The FPGA RX Elastic Buffer Requirement” on page 181.
TEMAC User Guide www.xilinx.com UG194 (v1.10) February 14, 2011