Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Additional Support Resources
User Guide Conventions
Acronyms
Additional Support Resources
Virtex-5 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
This document uses the following conventions.
Table 1-1 lists the acronyms and abbreviations that are used throughout this User Guide.
Table 1-1: Acronyms and Abbreviations in this User Guide
Acronym Definition
Byte PHY Name given to a particular Ethernet MAC clocking scheme described
in this User Guide
CRC Cyclic Redundancy Check
CSMA/CD Carrier Sense Multiple Access with Collision Detection
DA Destination Address (MAC frame)
DCR Device Control Register
DMA Direct Memory Access
EDK Embedded Development Kit (Xilinx software)
FCS Frame Check Sequence (MAC frame)
FIFO First In, First Out memory
FPGA Field Programmable Gate Array
GBIC Gigabit Interface Converter (optical transceiver)
Gb/s Gigabits per second
GMII Gigabit Media Independent Interface
GTP High-speed serial transceivers offered in the Virtex-5 LXT and SXT
platforms
GTX High-speed serial transceivers offered in the Virtex-5 FXT and TXT
platforms
IFG Interframe Gap (MAC frame)
TEMAC User Guide www.xilinx.com 13
UG194 (v1.10) February 14, 2011