Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 3: Client Interface When the host interface is used, all the address filter registers are accessible by software, using either the DCR bus or the generic host bus. The attribute settings of the registers can be overridden by the software through the host interface. Also, the four general address registers are programmed through the host interface. Client RX Data/Control Interface CLIENTEMAC#RXCLIENTCLKIN The AF generates the EMAC#CLIENTRXFRAMEDROP signal to inform the client that the destination MAC address of an incoming receive Ethernet frame does not match any of the acceptable addresses stored in the AF. This control signal is asserted regardless of whether the AF is enabled or disabled (promiscuous mode). Figure 3-23 shows the timing diagram when a frame matches a valid location in the AF (8-bit mode). EMAC#CLIENTRXDVLD EMAC#CLIENTRXD[7:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP CLIENTEMAC#RXCLIENTCLKIN Previous Frame Dropped n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Figure 3-23: Frame Matching Timing Diagram (8-Bit Mode) DA SA Current Frame Passed UG194_3_23_081806 Figure 3-24 shows the timing diagram when a frame matches a valid location in the AF (16-bit mode). PHYEMAC#RXCLK EMAC#CLIENTRXDVLD EMAC#CLIENTRXDVLDMSW EMAC#CLIENTRXD[15:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP Previous Frame Dropped n–5 n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6 Figure 3-24: Frame Matching Timing Diagram (16-Bit Mode) DA1, DA0 DA3, DA2 DA5, DA4 Current Frame Passed 72 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 DA UG194_3_24_081806 R
R CLIENTEMAC#RXCLIENTCLKIN Flow Control Block Flow Control Block Figure 3-25 shows the timing diagram when a frame fails to match a valid location in the AF (8-bit mode) and the frame drop signal is generated. EMAC#CLIENTRXDVLD EMAC#CLIENTRXD[7:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP CLIENTEMAC#RXCLIENTCLKIN Previous Frame Passed n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Figure 3-25: Frame Matching Failed Timing Diagram (8-Bit Mode) DA SA Current Frame Dropped UG194_3_25_081006 Figure 3-26 shows the timing diagram when a frame fails to match a valid location in the AF (16-bit mode) and the frame drop signal is generated. PHYEMAC#RXCLK EMAC#CLIENTRXDVLD EMAC#CLIENTRXDVLDMSW EMAC#CLIENTRXD[15:0] EMAC#CLIENTRXGOODFRAME EMAC#CLIENTRXFRAMEDROP Previous Frame Passed n–5 n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4 n+5 n+6 Figure 3-26: Frame Matching Failed Timing Diagram (16-Bit Mode) DA1, DA0 DA3, DA2 DA5, DA4 Current Frame Dropped The flow control block is designed to clause 31 of the IEEE Std 802.3-2005 standard. The Ethernet MAC can be configured to send PAUSE frames and to act upon the PAUSE frame's reception during full-duplex operation. These two behaviors can be configured asymmetrically (see “Configuration Registers,” page 88). TEMAC User Guide www.xilinx.com 73 UG194 (v1.10) February 14, 2011 DA UG194_3_26_081806
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
Page 17 and 18:
Introduction Key Features R Chapter
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R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71: R Address Filtering Address Filteri
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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