Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 4: Host/DCR Bus Interfaces
Table 4-11: Address Table Access (Word 0)
0x388
MSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GENERAL_ADDRESS[31:0]
Bit Description Default Value R/W
[31:0] General Address [31:0]. The general address bits [31:0] are temporarily
deposited into this register for writing into a general address register.
When a read from an address register has been performed, the address bits
[31:0] are accessible from this register.
The address is ordered so the first byte transmitted/received is the lowest
positioned byte in the register; for example, a MAC address of AA-BB-CC-
DD-EE-FF is stored in address [47:0] as 0xFFEEDDCCBBAA.
Table 4-12: Address Table Access (Word 1)
0x38c
MSB
96 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
LSB
All 0s R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RNW
RESERVED
ADDR
GENERAL_ADDRESS[47:32]
Bit Description Default Value R/W
General Address (Word 1)
[15:0] General Address [47:32]. The general address bits [47:32] are temporarily
deposited into this register for writing into a general address register.
[17:16] Address Table address. This two-bit vector is used to choose the general
address register to access.
00 = General Address Register 0
01 = General Address Register 1
10 = General Address Register 2
11 = General Address Register 3
[22:18] Reserved. –
[23] Address Table read enable (RNW). When this bit is 1, a general address
register is read. When this bit is 0, a general address register is written with
the address set in the general address table register.
[31:24] Reserved. –
LSB
All 0s R/W
All 0s R/W
0 R/W
R