Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
HOSTCLK
HOSTMIIMSEL
HOSTOPCODE[1]
HOSTADDR[8:0]
HOSTADDR[9]
HOSTRDDATA[31:0]
HOSTEMAC1SEL
Figure 4-5: Configuration Register Read Timing
Reading and Writing Address Filter Registers
UG194_4_05_051308
Using the Host Bus
Writing to registers in the Address Filter is the same as writing to configuration registers.
The timing diagram shown for writing to the Ethernet MAC Configuration Registers
(Figure 4-4) holds for Address Filter registers. HOSTADDR[9:0] takes the address of the
address filter register to be accessed, as described in Table 4-1.
To write a general address register, two write operations are required. First bits [31:0] of the
general address must be written into the General Address Table Access Word 0 register.
The upper bits [47:32] of the general address must then be written into the General
Address Table Access Word 1 register, along with the Address Table address and the RNW
bit at logic 0.
Reading the Unicast Address registers and the Address Mode register is also the same as
reading from configuration registers. The timing diagram shown for reading the Ethernet
MAC configuration registers (Figure 4-5) applies to accesses for these registers.
Figure 4-6 shows the timing diagram for reading the general address from one of the four
general address registers in the Address Table.
To read a general address register, a write must first be made to the General Address Table
Access Word 1 register. The RNW field is set to 1, and the Address Table address field
should be set with the register number to be read. The general address register data is
returned in HOSTRDDATA[31:0] as shown in Figure 4-6. The LSW is the general address
[31:0]. The MSW contains 0x0000 and the general address [47:32].
A Low on HOSTMIIMSEL indicates a configuration access. It must be held Low for an even
number of clock cycles during a read operation.
TEMAC User Guide www.xilinx.com 99
UG194 (v1.10) February 14, 2011