Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
Reduced Gigabit Media Independent Interface (RGMII)
At 1 Gb/s, all external logic is clocked at 125 MHz. At 100 Mb/s and 10 Mb/s, the logic is
clocked at 25 MHz and 2.5 MHz, respectively. To maintain the correct data rate at the client
interface, clock enable signals are output on EMAC#CLIENTTXCLIENTCLKOUT for the
transmitter logic, and EMAC#CLIENTRXCLIENTCLKOUT for the receiver logic. These
signals are High during 1 Gb/s operation and toggle on each clock edge at slower speeds.
These are used to enable the client interface logic.
Due to the timing relationship between the RGMII transmit clock and the internal client
clock signals, the TX_ACK signal (CLIENTEMAC#TXACK) is registered at the output of the
Ethernet MAC when operating at speeds below 1 Gb/s. At 1 Gb/s, the register is
bypassed.
RGMII_TXC is derived from the Ethernet MAC by routing the
EMAC#PHYTXGMIIMIICLKOUT port to an IOB DDR output register, followed by an
ODELAY element and an OBUF (which is then connected to the PHY). The ODELAY
element is used to generate 2 ns of skew required between RGMII_TXC and RGMII_TXD at
the FPGA device pads. This delay is specified in the
Hewlett Packard RGMII Specification, v2.0 to provide setup and hold times on the external
interface.
RGMII_RXC is generated by the PHY and connected to PHYEMAC#RXCLK via an IBUFG
and a BUFG. Fixed-mode IDELAYs are instantiated on the RGMII clock and data lines.
These are set to sample a 1 ns setup, 1 ns hold window at the device pads. RGMII_RXC
drives all receive logic. The CLIENTEMAC#DCMLOCKED port must be tied High.
This clocking scheme requires two fewer BUFGs than the default scheme detailed in
Figure 6-15.
TEMAC User Guide www.xilinx.com 163
UG194 (v1.10) February 14, 2011