Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
1000BASE-X PCS/PMA
REFCLKOUT output port of the RocketIO serial transceiver. This clock is then routed to
the CLKIN input of a DCM. CLK0 of the DCM is connected to global clock routing using a
BUFG, as illustrated in Figure 6-22. The 125 MHz output of the BUFG is connected to the
PHYEMAC#MIITXCLK and PHYEMAC#RXCLK ports of the Ethernet MAC. It is also
used to clock both receiver and transmitter logic for the 16-bit Ethernet MAC client
interface.
The global clock sourced from DCM CLKFX, running at 250 MHz, must be routed back to
the Ethernet MAC through the input ports CLIENTEMAC#RXCLIENTCLKIN and
CLIENTEMAC#TXCLIENTCLKIN. This clock is also connected to the
PHYEMAC#GTXCLK input of the Ethernet MAC and the USRCLK inputs of the
transceiver.
The PLLLKDET signal from the RocketIO serial transceiver (indicating that its internal
PLLs have locked) is ANDed with the locked signal from the DCM and routed to the
CLIENTEMAC#DCMLOCKED input port of the Ethernet MAC. This ensures that the state
machines of the Ethernet MAC are held in reset until the RocketIO serial transceiver has
locked and all clocks are running cleanly.
As described in “Ethernet MAC Clock Generation,” page 206, the following clock signals
are unused and can be left unconnected:
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#PHYTXGMIIMIICLKOUT
EMAC#CLIENTTXCLIENTCLKOUT
1000BASE-X PCS/PMA Clock Management (TXT and FXT Devices)
8-Bit Data Client
Figure 6-23 shows the clock management used with the 1000BASE-X PCS/PMA interface
when the Ethernet MAC client is used with a 8-bit data client in a TXT and FXT device.
TEMAC User Guide www.xilinx.com 171
UG194 (v1.10) February 14, 2011